IP Library Patent Application 10895973
Patent Application
App. No. 10/895,973

Floating pin lamination plate system for multilayer circuit boards

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Quick Facts
Patent No.
US None
App. No.
10/895,973
Abstract

A lamination plate system for registering printed circuit board layers in a lamination press, the layers having a plurality of corresponding registration holes formed therein, the system comprising: a plurality of respective pins for passing through the registration holes to register the layers vertically, each pin having a head and a shaft; and, top and bottom caul plates having a plurality of corresponding holes and bores formed therein, respectively, each hole and bore for receiving the shaft and head of a pin, respectively; wherein the pins, holes, and bores are sized to allow for horizontal movement of the layers when positioned between the top and bottom caul plates during lamination.

Claims (13)

1 . A lamination plate system for registering printed circuit board layers in a lamination press, the layers having a plurality of corresponding registration holes formed therein, the system comprising:

a plurality of respective pins for passing through the registration holes to register the layers vertically, each pin having a head and a shaft; and,

top and bottom caul plates having a plurality of corresponding holes and bores formed therein, respectively, each hole and bore for receiving the shaft and head of a pin, respectively;

wherein the pins, holes, and bores are sized to allow for horizontal movement of the layers when positioned between the top and bottom caul plates during lamination.

2 . The system of claim 1 wherein the registration holes in the layers correspond to ones of respective holes and bores in the top and bottom caul plates.

3 . The system of claim 2 and further comprising first and second separator plates positioned between the top and bottom caul plates, respectively, and the layers, the first and second separator plates having holes formed therein corresponding to the holes formed in the top caul plate.

4 . The system of claim 3 wherein the holes formed in the first and second separator plates have a lesser diameter than the holes formed in the top caul plate.

5 . The system of claim 3 and further comprising first and second sheets positioned between the first and second separator plates, respectively, and the layers, the first and second sheets having holes formed therein corresponding to the registration holes formed in the layers.

6 . The system of claim 5 wherein the first and second sheets are aluminium sheets.

7 . The system of claim 1 wherein the circuit board layers include at least one of flexible circuit board layers and rigid circuit board layers.

8 . The system of claim 1 wherein the holes and bores in the top and bottom caul plates are arranged in a grid pattern.

9 . The system of claim 8 wherein the grid pattern has square cells.

10 . The system of claim 8 wherein the square cells are one inch square.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2012
From: JPMORGAN CHASE BANK, N.A.
To: DDI TORONTO CORP.
Reel/Frame 028426/0333 →
SECURITY AGREEMENT Recorded Nov 30, 2010
From: DDI TORONTO CORP.
To: JPMORGAN CHASE BANK N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025321/0444 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2005
From: HOEPPEL, GARY A.; MCGARRY, ROBERT P., JR.
To: CORETEC INC.
Reel/Frame 016496/0632 →