Semiconductor memory device with bit line of small resistance and manufacturing method thereof
View Patent ↗A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.
1. A semiconductor memory device, comprising:
plural linear word lines formed on a semiconductor substrate;
plural linear bit lines running at right angles to said word lines;
a memory transistor formed between said bit lines in said semiconductor substrate and employing said word lines as a gate electrode; and
an interlayer insulating film formed on said memory transistor, wherein
each of said bit lines is composed of
a diffusion bit line formed in said semiconductor substrate and
a metal bit line formed with being buried in said interlayer insulating film in a linear pattern and connected with said diffusion bit line between said word lines, wherein said metal bit line overlies said word lines and said diffusion bit line is formed in a continuous linear pattern under said metal bit line on a lower side of said word lines.
2. The semiconductor memory device according to claim 1 , wherein
a gate insulating film under said gate electrode is an ONO (Oxide Nitride Oxide) film in said memory transistor.
3. The semiconductor memory device according to claim 1 , further comprising:
an insulating film on diffusion bit line formed in a linear pattern on an upper part of said diffusion bit line, wherein
said metal bit line goes through said insulating film on diffusion bit line and is connected with said diffusion bit line between said word lines.
4. The semiconductor memory device according to claim 3 , wherein
a width of said diffusion bit line is narrower than a width of said insulating film on diffusion bit line.
5. The semiconductor memory device according to claim 1 , wherein
a memory cell array formed with a plurality of said memory transistors has a fieldless array structure.