Trench-type MOSFET having a reduced device pitch and on-resistance
View Patent ↗A trench-type lateral power MOSFET is manufactured by forming an n − -type diffusion region, which will be a drift region, on a p − -type substrate; selectively removing a part of substrate and a part of n − -type diffusion region to form trenches; forming a gate oxide film of 0.05 μm in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p − -type base region and an n + -type diffusion region, which will be a source region, in the bottom of each trench; and forming an n + -type diffusion region, which will be a drain region, in the surface portion of n − -type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.
1. A method of manufacturing a semiconductor device comprising the steps of:
forming a drift region of a second conductivity type on a semiconductor substrate of a first conductivity type;
removing selectively a part of the drift region and a part of the semiconductor substrate, whereby to form trenches;
forming a gate insulation film with uniform thickness along the inner side walls and the bottom surface of each trench;
forming a first electrical conductor on the gate insulation film;
forming an oxide film on the first electrical conductor;
removing selectively the region of the oxide film corresponding to an active region, whereby to expose the first electrical conductor in the region corresponding to the active region;
etching back the first electrical conductor in the region corresponding to the active region such that the first electrical conductor is remaining along the side walls of the trench;
forming a base region of the first conductivity type and a source region of the second conductivity type in the bottom portion of the trench;
forming a first interlayer insulation film in the trench;
removing the bottom portion of the first interlayer insulation film in the region corresponding to the active region and the portion of the gate insulation film below the removed bottom portion of the first interlayer insulation film, whereby to expose the source region; and
forming a second electrical conductor in the trench, the second electrical conductor being connected electrically to the source region.
2. The method according to claim 1 , further comprising the steps of:
forming a drain region of the second conductivity type in the surface portion of the drift region;
forming a second interlayer insulation film on the surface of the semiconductor substrate;
boring contact holes in the first interlayer insulation film and the second interlayer insulation film;
forming a gate electrode connected electrically to the first electrical conductor;
forming a source electrode connected electrically to the second electrical conductor; and
forming a drain electrode connected electrically to the drain region.
3. The method according to claim 1 , wherein the step of etching back comprises over etching the first electrical conductor in the region corresponding to the active region such that the upper end face of the first electrical conductor is positioned at a level lower than the surface of the semiconductor substrate.