Field-effect type semiconductor device for power amplifier

1. A method of fabricating a field-effect type semiconductor device, comprising the steps of:

forming a first SiGe layer having a first conductivity-type and high impurity concentration on a major surface of an Si substrate having the first conductivity-type;

forming a second SiGe layer having the first conductivity-type and low impurity concentration on a major surface of said first SiGe layer;

forming an Si layer having low impurity concentration on a major surface of said second SiGe layer, thus completing a semiconductor multi-layer structure;

forming a groove for isolating active regions in a major surface of said semiconductor multi-layer structure;

embedding an insulating material in said groove;

impaling an impurity into said active region;

forming a gate insulating film on a surface of said active region;

forming a gate electrode on said gate insulating film;

forming a drain offset region in said active region in self-alignment with said gate electrode;

forming, in said active region, a drain region being separated from the edge of said gate electrode, contacting said drain offset region in self-alignment with said gate electrode and having an impurity concentration higher than that of said offset region, and a source region in self-alignment with said gate electrode;

exposing said first SiGe layer or said substrate in a region near said source region; and

connecting said exposed portion and said source region by metal or metal silicide.

2. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said first conductivity-type is P-type and said second conductivity-type is N-type.

3. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said first conductivity-type is N-type and said second conductivity-type is P-type.

4. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said first SiGe layer has a thickness of not less than 0.5 μm and not greater than 3.0 μm.

5. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said second SiGe layer has a thickness of not less than 0.5 μm and not greater than 2.5 μm.

6. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein a crystal defect region is formed in said Si substrate or said first SiGe layer, and an interface between said first and second SiGe layers and said defect region do not contact each other.

7. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said second SiGe layer has a Ge content ratio of not less than 5% and not greater than 50% and an interface between said first and second SiGe layers has the same Ge content ratio as that of said second SiGe layer.

8. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said first SiGe layer has a Ge content ratio that is small at an interface to said Si substrate and increases in a direction of film thickness.

9. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said Si layer has a thickness of not less than 2 nm and not greater than 70 nm.

10. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said first SiGe layer has a peak value of impurity concentration that is not less than 1×10 19 /cm 3 .

11. A method of fabricating a field-effect type semiconductor device according to claim 1 , wherein said gate electrode includes a polycrystalline Si layer or polycrystalline SiGe layer and a metal silicide layer formed on said polycrystalline Si layer or polycrystalline SiGe layer.