Semiconductor integrated circuit device and process for producing the same
View Patent ↗A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201 , floating gates 203 b formed on semiconductor substrate 200 through an insulator film 202 , control gates 211 a formed on floating gates 203 b through nitrogen-introduced silicon oxide film 210 a and third gates 207 a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207 a thus formed is made lower than that of floating gates 203 b , has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.
1. A process for producing a nonvolatile memory device, which comprises the steps of:
forming third gates on a first insulator film disposed on a silicon substrate;
forming a second insulator film covering the third gates;
forming a first pattern to act as floating first gates in gaps formed between the third gates; and
forming control second gates above the floating first gates and the third gates, the height of the upper surfaces of the third gates thus formed being made lower than that of the upper surface of the first pattern,
wherein in the forming of the third gates, a plurality of third gates are formed in a stripe shape and are formed parallel to each other,
and wherein in the forming of the first pattern, the floating first gates and the third gates are formed so as to be provided alternately.
2. A process according to claim 1 , wherein the first pattern is formed by any one of the following methods:
a first method including forming a polysilicon film to completely fill the gaps, and dry etching the polysilicon film;
a second method including forming a polysilicon film to completely fill the gaps, and polishing the poly-silicon film by chemical mechanical polishing, followed by dry etching;
a third method including forming a polysilicon film so as not to completely fill the gaps, and polishing the polysilicon film by chemical mechanical polishing;
a fourth method including forming a polysilicon film so as not to completely fill The gaps, forming a photoresist film to fill the gaps, and dry etching the photoresist film and the polysilicon film; and
a fifth method including forming a polysilicon film so as not to completely fill the gaps, depositing a silicon oxide film to fill the gaps, and polishing the silicon oxide film and the polysilicon film by chemical mechanical polishing.
3. A process according to claim 1 , wherein the third gates are self-aligned to the first gates.
4. A process according to claim 1 , wherein the first gates are self-aligned to the third gates.