Methods of forming a P-well in an integrated circuit device
View Patent ↗The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.
1. A method of forming a P-well region for a PNP bi-polar transistor, comprising:
performing a first ion implantation process to form a first p-doped region in a portion of an active layer of a substrate to form a portion of a buried layer for the PNP transistor;
forming a first layer of epitaxial material above said active layer;
forming a second p-doped region in said first layer of epitaxial material;
after forming said second p-doped region, forming a second layer of epitaxial material above said first layer of epitaxial material;
after forming said second layer of epitaxial material, forming a third p-doped region in said second layer of epitaxial material; and
after forming said third p-doped region, performing at least one heat treating process to cause said second and third p-doped regions to migrate toward one another and thereby define a portion of said P-well, wherein said at least one heat process is performed until said second and third p-doped regions engage one another and said second p-doped region engages said first p-doped region.
2. The method of claim 1 , wherein said first and second layers of epitaxial material are comprised of at least one of silicon and germanium.
3. The method of claim 1 , wherein said step of forming said second p-doped region comprises performing a second ion implantation process to form said second p-doped region.
4. The method of claim 3 , wherein said step of forming said third p-doped region comprises performing a third ion implantation process to form said third p-doped region.
5. The method of claim 1 , wherein said first layer of epitaxial material has a thickness of approximately 12-18 μm.
6. The method of claim 1 , wherein said second layer of epitaxial material has a thickness of approximately 6-12 μm.
7. The method of claim 1 , wherein said second p-doped region is comprised of boron.
8. The method of claim 1 , wherein said third p-doped region is comprised of boron.
9. The method of claim 1 , wherein said second p-doped region is formed by performing a second ion implantation process using boron at a dopant dose of approximately 4×10 11 -8×10 11 ions/cm 2 and at an implant energy of approximately 60-100 keV.
10. The method of claim 1 , wherein said third p-doped region is formed by performing a third ion implantation process using boron at a dopant dose of approximately 4×10 11 -8×10 11 ions/cm 2 and at an implant energy of approximately 60-100 keV.
11. The method of claim 1 , further comprising forming a first layer of silicon dioxide above said first layer of epitaxial material prior to forming said second p-doped region.
12. The method of claim 1 , further comprising forming a second layer of silicon dioxide above said second layer of epitaxial material prior to forming said third p-doped region.
13. A method of forming a P-well region for a PNP bi-polar transistor, comprising:
performing a first ion implantation process to form a first p-doped region in a portion of an active layer of a silicon-on-insulator structure to form a portion of a buried layer for the PNP transistor;
forming a first layer of epitaxial silicon above said active layer;
forming a second p-doped region in said first layer of epitaxial silicon;
after forming said second p-doped region, forming a second layer of epitaxial silicon above said first layer of epitaxial silicon;
after forming said second layer of epitaxial material, forming a third p-doped region in said second layer of epitaxial silicon; and
after forming said third p-doped region, performing at least one heat treating process to cause said second and third p-doped regions to migrate toward one another and thereby define a portion of said P-well, wherein said at least one heat process is performed until said second and third p-doped regions engage one another and said second p-doped region engages said first p-doped region.
14. The method of claim 13 , wherein said step of forming said second p-doped region comprises performing a second ion implantation process to form said second p-doped region.
15. The method of claim 14 , wherein said step of forming said third p-doped region comprises performing a third ion implantation process to form said third p-doped region.
16. The method of claim 13 , wherein said first layer of epitaxial silicon has a thickness of approximately 12-18 μm.
17. The method of claim 13 , wherein said second layer of epitaxial silicon has a thickness of approximately 6-12 μm.
18. The method of claim 13 , wherein said second p-doped region is formed by performing a second ion implantation process using boron at a dopant dose of approximately 4×10 11 -8×10 11 ions/cm 2 and at an implant energy of approximately 60-100 keV.
19. The method of claim 18 , wherein said third p-doped region is formed by performing a third ion implantation process using boron at a dopant dose of approximately 4×10 11 -8×10 11 ions/cm 2 and at an implant energy of approximately 60-100 keV.
20. The method of claim 13 , further comprising forming a first layer of silicon dioxide above said first layer of epitaxial silicon prior to forming said second p-doped region.
21. The method of claim 13 , further comprising forming a second layer of silicon dioxide above said second layer of epitaxial silicon prior to forming said third p-doped region.
22. A method of forming a P-well region for a PNP bi-polar transistor, comprising:
performing a first ion implantation process to form a first p-doped region in a portion of an active layer of a silicon-on-insulator structure to form a portion of a buried layer for the PNP transistor;
forming a first layer of epitaxial silicon above said active layer, said first layer of epitaxial silicon having a thickness of approximately 12-18 μm;
performing a second ion implantation process to form a second p-doped region in said first layer of epitaxial silicon;
after forming said second p-doped region, forming a second layer of epitaxial silicon above said first layer of epitaxial silicon, said second layer of epitaxial silicon having a thickness of approximately 6-12 μm;
after forming said second layer of epitaxial material, performing a third ion implantation process to form a third p-doped region in said second layer of epitaxial silicon; and
after forming said third p-doped region, performing at least one heat treating process to cause said second and third p-doped regions to migrate toward one another and thereby define a portion of said P-well, wherein said at least one heat process is performed until said second and third p-doped regions engage one another and said second p-doped region engages said first p-doped region.
23. The method of claim 22 , wherein said second ion implantation process is performed using boron at a dopant dose of approximately 5×10 11 ions/cm 2 and at an implant energy of approximately 80 keV.
24. The method of claim 22 , wherein said third ion implantation process is performed using boron at a dopant dose of approximately 5×10 11 ions/cm 2 and at an implant energy of approximately 80 keV.
25. The method of claim 22 , further comprising forming a first layer of silicon dioxide above said first layer of epitaxial silicon prior to forming said second p-doped region.
26. The method of claim 22 , further comprising forming a second layer of silicon dioxide above said second layer of epitaxial silicon prior to forming said third p-doped region.