IP Library Patent Application 10899659
Patent Application
App. No. 10/899,659

Multiple gate semiconductor device and method for forming same

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Patent No.
US None
App. No.
10/899,659
Abstract

In accordance with an embodiment of the invention, a FinFET device is disclosed which comprises a strained silicon channel layer formed on, at least, the sidewalls of a strain-relaxed silicon-germanium body.

Claims (27)

1 . A semiconductor device comprising:

a substrate;

a first contact region and a second contact region formed on the substrate;

a semiconductor fin in between and connecting the first contact region and the second contact region, the semiconductor fin having a body comprising a strain-relaxed material, the body having a surface, the surface not facing the substrate.

2 . The semiconductor device of claim 1 wherein the strain-relaxed material is an Si 1-y Ge y alloy with 0<y<1.

3 . The semiconductor device of claim 2 further comprising a layer, the layer at least partially overlapping the body, and the layer being lattice mismatched with the underlying strain-relaxed body.

4 . The semiconductor device of claim 3 wherein the overlapping layer at least covers those parts of the surface of the body, which are oblique to the substrate.

5 . The semiconductor device of claim 3 wherein the overlapping layer covers substantially the entire surface.

6 . The semiconductor device of claim 3 further comprising a gate, which at least partially, straddles the semiconductor fin.

7 . The semiconductor device of claim 6 wherein the first contact region is a source region and the second contact region is a drain region of a Field Effect Transistor.

8 . The semiconductor device of claim 3 wherein the layer comprises one or more elements selected from the atomic groups III, IV or V.

9 . The semiconductor device of claim 8 , wherein one of the elements is germanium.

10 . The semiconductor device of claim 8 , wherein one of the elements is silicon.

11 . The semiconductor device of claim 8 , wherein the layer comprises AlAs, GaAs or AlGaAs.

12 . The semiconductor device of claim 1 further comprising a layer, the layer at least partially overlapping the body, and the layer being lattice mismatched with the underlying strain-relaxed body.

13 . A method for manufacturing a semiconductor device having a fin, the fin comprising a strain-relaxed body, comprising:

providing a substrate, wherein the substrate comprises a source, a drain, and a fin in between, and connecting, the source and the drain, the fin having a body being formed of a first semiconductor material; the fin having a surface not facing the substrate,

depositing, at least on those parts of the surface which are oblique to the substrate, an alloy layer comprising a second and a third semiconductor material;

at least partially oxidizing the alloy layer thereby forming an oxide of the second material and thereby converting the body of a first semiconductor material in to an alloy of the first and the third semiconductor materials, the alloy being a strain-relaxed material; and

removing the oxide of the second semiconductor material.

14 . The method of claim 13 further comprising the step of forming a layer comprising a fourth semiconductor material, the layer at least partially overlaying the body, and the layer being lattice mismatched with the underlying strain-relaxed body.

15 . The method of claim 14 wherein

the layer at least covers those parts of the surface which are oblique to the substrate.

16 . The method of claim 14 wherein the first and/or the second semiconductor materials comprise silicon.

17 . The method of claim 14 wherein the third semiconductor material comprises germanium.

18 . The method of claim 14 wherein the fourth semiconductor material is selected from the atomic groups III, IV or V.

19 . The method of claim 18 wherein the fourth semiconductor material comprises silicon.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2009
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC VZW), A BELGIUM CORPORATION
To: IMEC
Reel/Frame 023419/0154 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2004
From: KOTTANTHARAYIL, ANIL; LOO, ROGER
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC VZW), A BELGIUM CORPORATION
Reel/Frame 015762/0060 →