Arrangement for generating a clock signal for a sigma-delta analog-to-digital converter
In a method for generating a scanning clock signal (S) for scanning an analog signal (Ua) for an analog-to-digital converter ( 20 ) operating according to the sigma-delta method, a variable period (T; T*) of the power supply system (PL) is ascertained in time units of a system clock signal (C), and the scanning clock signal (S) is generated by distributing a constant number K of pulses over the ascertained period (T; T*), so that the frequency of the scanning clock signal (S) is an integer multiple of the frequency of the power supply system (PL). The method is essentially able to be carried out by an accumulator unit ( 4 ) connected to a counter ( 3 ) and makes possible the advantage that during the analog-to-digital conversion a mains hum contained in the analog signal (Ua) is suppressed.
1. Method for generating a scanning clock signal for scanning an analog signal for an analog-to-digital converter operating according to the sigma-delta method, comprising the method steps of:
ascertaining a variable period of the power supply system in time units of a system clock signal, and
generating the scanning clock signal by distributing a constant number K of pulses over the ascertained period, so that the frequency of the scanning clock signal is an integer multiple of the frequency of the power supply system.
2. Method according to claim 1 , wherein the number K is equal to the value of the decimation rate of the analog-to-digital converter.
3. Apparatus for carrying out a method according to claim 1 , the apparatus comprising:
a counter able to be clocked by the system clock signal, a signal derived from the power supply system being able to be conducted at an input of the counter, so that the period of the power supply system is able to be counted in time units of the system clock signal by the counter, and
an accumulator unit, able to be clocked by the system clock signal, including an adding register, to which the counted period is able to be allocated as a counting limit and in which the current value of the adding register is able to be increased by a constant value W with every pulse of the system clock signal, the accumulator unit including an output for the scanning clock signal at which a pulse is able to be generated if the counting limit is exceeded.
4. Apparatus according to claim 3 , further comprising a digital filter, connected between the counter and the accumulator unit, by which the period counted by the counter is able to be filtered.
5. Apparatus according to claim 3 , wherein the value W is equal to the value of the decimation rate of the analog-to-digital converter.
6. Apparatus according to claim 3 , wherein the value W is equal to double the value of the decimation rate of the analog-to-digital converter.
7. Apparatus according to claim 6 , further comprising a frequency divider, connected downstream from the accumulator unit, by which the frequency of the output signal of the accumulator unit is able to be halved.