Delay circuit and delay synchronization loop device
View Patent ↗A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.
1. A delay circuit comprising:
a first delay line circuit having a plurality of stages of delay units;
a second delay line circuit having a plurality of stages of delay units;
a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;
said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal;
the delay unit of each stage of said second delay line circuit, including a logic circuit receiving an output signal of the transfer circuit associated with the delay unit and an output signal of a preceding stage and outputting the result of logical operation of the input signals to a following stage,
one of a plurality of the transfer circuits, receiving respective outputs of odd-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal;
one of a plurality of transfer circuits, receiving respective outputs of even-numbered stages of delay units of said first delay line circuit, is selected by a corresponding control signal; and
the rise timing and the fall timing of an output signal of said second delay line circuit are variably set with respect to the rising and fall of the signal supplied to said first delay line circuit.
2. A signal generating device comprising the delay circuit according to claim 1 , wherein the rising and falling edges of the output signal are varied independently relative to the rising and falling of the input signal.
3. A delay circuit comprising:
a first delay line circuit having a plurality of stages of delay units;
a second delay line circuit having a plurality of stages of delay units;
a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;
said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal;
the delay unit of each stage of said second delay line circuit, including a logic circuit receiving an output signal of the transfer circuit associated with the delay unit and an output signal of a preceding stage and outputting the result of logical operation of the input signals to a following stage,
in case the control signal supplied to the transfer circuit associated with a given one of the even-numbered stages and to the transfer circuit associated with a given one of the odd-numbered stages is activated, the control signals supplied to respective transfer circuits downstream of said transfer circuit are activated.
4. A delay circuit comprising:
a first delay line circuit having a plurality of stages of delay units;
a second delay line circuit having a plurality of stages of delay units;
a third delay line circuit having a plurality of stages of delay units;
a first set of plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits controlling the transfer of the outputs of said respective stages of delay units of said first delay line circuit to associated stages of the delay units of said second delay line circuit based on respective input control signals; and
a second set of plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits controlling the transfer of the outputs of the respective stages of said delay units of said first delay line circuit to associated stages of the delay units of said third delay line circuit based on respective input control signals;
the delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay unit to output the resultant inverted signal;
the delay unit of each stage of said second delay line circuit including a logic circuit receiving an output signal of the transfer circuit of the first set of transfer circuits associated with said delay unit and an output signal of a preceding stage to output the result of the logical operation on the input signals to a following stage;
the delay unit of each stage of said third delay line circuit including a logic circuit receiving an output signal of the transfer circuit of the second set of transfer circuits associated with said delay unit and an output signal of a preceding stage to output the result of the logical operation on the input signals to a following stage.
5. A delay locked loop device comprising:
a first delay line circuit receiving an input clock signal;
a second delay line circuit for performing fine phase adjustment of an output signal based on the rising of the clock signal output from said first delay line circuit;
a third delay circuit for performing fine phase adjustment of an output signal based on the falling of the clock signal output from said first delay line circuit;
a multiplexing circuit receiving an output signal of said second delay line circuit and an output signal of said third delay circuit and outputting an output clock signal multiplexed from said two output signals supplied thereto;
a first phase detection circuit receiving said input clock signal and an output clock signal of said multiplexing circuit to detect the phase difference of the rising edges thereof;
a second phase detection circuit receiving said input clock signal and an output clock signal of said multiplexing circuit to detect the phase difference of the falling edges thereof;
a first counter for counting the result of phase detection by said first phase detection circuit;
a second counter for counting the result of phase detection by said second phase detection circuit;
a first selection circuit for outputting a control signal for adjusting the rise timing in said first delay line circuit based on a count output of said first counter; and
a second selection circuit for outputting a control signal for adjusting the fall timing in said first delay line circuit based on a count output of said second counter; wherein
said first delay line circuit is a delay circuit comprising:
a plurality of stages of delay units;
a plurality of transfer circuits provided in association with respective stages of the delay units of said first delay line circuit, said transfer circuits respectively receiving outputs of said stages of the delay units of said first delay line circuit to control the transfer of the outputs of said delay units to associated stages of the delay units of said second delay line circuit;
said delay unit of each stage of said first delay line circuit inverting a signal supplied to said delay units and outputting the inverted signal.
6. The delay locked loop device according to claim 5 , wherein
said first delay line circuit outputs a signal with plural rising edges of respective different phases, generated from said input signal, and another signal with plural falling edges of respective different phases, generated from an inverted version of said input signal.
7. A semiconductor storage device including the delay locked loop device as defined in claim 5 , said semiconductor storage device comprising
a data multiplexer for selecting input parallel readout data for outputting a serial output, based on the rising and falling edges of a clock signal output from said data multiplexer, and an output buffer receiving the output of said multiplexer to output said output at a data output terminal thereof.
8. The semiconductor storage device according to claim 7 , further comprising:
a dummy circuit of a delay time equivalent to the delay time of said data multiplexer; wherein
said dummy circuit receives an output clock signal from said multiplexer to output a feedback clock signal and wherein said feedback clock signal is supplied from said dummy circuit to said first and second phase detection circuits.