Variable frequency generator
View Patent ↗A digital circuit generates very precise varying clock frequencies for applications that can tolerate a small degree of jitter but require exact longer term frequencies, e.g. a video clock for a laser printer. Some subpixel jitter is acceptable, but the overall pixel rate remains exact and consistent. In some applications, the jitter may be desirable to smear the EMI spectrum. For example, if the high frequency input clock is modulated, the edges of the video clock will also be modulated yet remain within the jitter and frequency specification.
1. A circuit comprising:
a frequency request generator, receiving a reference signal, a dithered signal, and a beam detect signal;
deltaF table bidirectionally connected to the frequency request generator;
a variable frequency generator, connected to the frequency request generator, generating a variable frequency output; and
configuration registers transceiving data and control signals with the frequency request generator, the variable frequency generator, and the deltaF table.
2. A circuit, as defined in claim 1 , further comprising a modulated analog phase lock loop, receiving the reference signal, generating the dithered signal.
3. A circuit, as defined in claim 2 , the variable frequency generator comprising:
a predictor connected to the frequency request generator;
a corrector, connected to the frequency request generator, receiving a predictor output;
an accumulator, receiving a corrector output;
an output generator, generating the variable frequency output, receiving an accumulator output;
wherein the predictor, corrector, accumulator, and output generator transceive the data control signals with the configuration registers and receive the reference signal, and the dithered signal.
4. A circuit, as defined in claim 2 , the variable frequency generator comprising:
predictive means, connected to the frequency request generator, generating a first output signal indicative of the average number of dithered periods to remove per reference period;
corrective means, connected to the frequency request generator, generating a second output signal indicative of the fractional number of dithered periods to remove each reference period;
an adder receiving the first and second outputs, generating a third output signal indicative of the number of clocks to remove per reference period;
a scale factor;
a multiplier, receiving the scale factor and the third output signal, generating a fourth output signal indicative of the fractional number of clocks to remove each dithered clock period;
an accumulator, receiving the fourth output signal, operative to count the fractional number of dithered periods, removing a dithered period when an integer has been reached.
5. A circuit, as defined in claim 4 , the predictive means comprising:
a counter for counting the average number of dithered periods for the sample of the reference signal; and
a subtractor, connected to the frequency request generator and the counter, generating the first output signal.
6. A circuit, as defined in claim 4 , the corrective means comprising:
error means for measuring the error from the last sample, connected to the frequency request generator, having an error signal;
a scale factor register value; and
a multiplier, receiving the error signal and the scale factor, generating the second output signal.
7. A circuit, as defined in claim 1 , the variable frequency generator comprising:
a predictor connected to the frequency request generator;
a corrector, connected to the frequency request generator, receiving a predictor output;
an accumulator, receiving the corrector output;
an output generator, generating the variable frequency output, receiving the accumulator output;
wherein the predictor, corrector, accumulator, and output generator transceive the data control signals with the configuration registers and receive the reference signal, and the dithered signal.
8. A circuit, as defined in claim 1 , the variable frequency generator comprising:
predictive means, connected to the frequency request generator, generating a first output signal indicative of the average number of dithered periods to remove per reference period;
corrective means, connected to the frequency request generator, generating a second output signal indicative of the fractional number of dithered periods to remove each reference period;
an adder receiving the first and second outputs, generating a third output signal indicative of the number of clocks to remove per reference period;
a scale factor;
a multiplier, receiving the scale factor and the third output signal, generating a fourth output signal indicative of the fractional number of clocks to remove each clock period;
an accumulator, receiving the fourth output signal, operative to count the fractional number of dithered periods, removing a dithered period when an integer has been reached.
9. A circuit, as defined in claim 8 , the predictive means comprising:
a counter for counting the average number of dithered periods for the sample of the reference signal; and
a substractor, connected to the frequency request generator and the counter, generating the first output signal.
10. A circuit, as defined in claim 8 , the corrective means comprising:
error means for measuring the error from the last sample, connected to the frequency request generator, having an error signal;
a scale factor register value; and
a multiplier, receiving the error signal and the scale factor, generating the second output signal.