Method of removing spacers and fabricating MOS transistor
View Patent ↗A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.
1. A method of removing spacers after forming a metal-oxide-semiconductor (MOS) transistor, wherein the MOS transistor comprises a gate structure over a substrate, spacers on the sidewalls of the gate structure and a source region and a drain region in the substrate beside the gate structure; the method comprising the step of performing a wet etching process in a dark environment.
2. The method of claim 1 , wherein the material constituting the spacers comprises silicon nitride.
3. The method of claim 2 , wherein the etching agent for performing the wet etching process comprises phosphoric acid.
4. A method of fabricating a metal-oxide-semiconductor (MOS) transistor, the method comprising:
providing a substrate;
forming a gate structure over the substrate, wherein the gate structure comprises a gate dielectric layer and a gate layer sequentially stacked over the substrate;
forming spacers on the sidewalls of the gate structure;
forming a source region and a drain region in the substrate beside the gate structure;
performing a wet etching process in a dark environment to remove the spacers on the sidewalls of the gate structure; and
forming a strain layer over the substrate to cover the gate structure and the substrate, wherein the strain layer is used for adjusting the lattice structure of the substrate.
5. The method of claim 4 , wherein the material constituting the spacers comprises silicon nitride.
6. The method of claim 5 , wherein the etching agent for performing the wet etching process comprises phosphoric acid.
7. The method of claim 4 , wherein the material constituting the strain layer comprises silicon oxide or silicon nitride.
8. The method of claim 4 , wherein after forming the gate structure but before forming the spacers, the method further comprises forming a lightly doped drain (LDD) region in the substrate beside the gate structure.