IP Library Granted Patent US 7,193,452
Granted Patent B2
US 7,193,452 · App. 10/905,660 · Granted Mar 20, 2007

Temperature-compensated bias circuit for power amplifier

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Quick Facts
Patent No.
US 7,193,452
App. No.
10/905,660
Granted
Mar 20, 2007
Kind
B2
Abstract

Provided is a temperature-compensated bias circuit for a power amplifier, in which a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q 3 ) and an emitter terminal of the third transistor is connected to a first diode (D 1 ). The temperature-compensated bias circuit includes a second resistor (R 1 ) connected to the reference voltage, a third resistor (R 2 ) connected to the second resistor in series, a fourth resistor (Rc) having one terminal connected to the reference voltage, a fifth resistor (Re) having one terminal connected to ground, a bias transistor (Q 4 ) having a base terminal connected to a contact point (VS) between the second resistor and the third resistor, a collector terminal connected to the other terminal of the fourth resistor, and an emitter terminal connected to the other terminal of the fifth resistor, and a sixth resistor (Rf) connected between a collector terminal of the third transistor and a collector terminal of the bias transistor.

Claims (40)

1. A temperature-compensated bias circuit for a power amplifier comprising:

a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q 3 ) and an emitter terminal of the third transistor is connected to a first diode (D 1 );

a second resistor (R 1 ) connected to the reference voltage;

a third resistor (R 2 ) connected to the second resistor in series;

a fourth resistor (Rc) having one terminal connected to the reference voltage;

a fifth resistor (Re) having one terminal connected to ground;

a bias transistor (Q 4 ) having a base terminal connected to a contact point (VS) between the second resistor and the third resistor, a collector terminal connected to the other terminal of the fourth resistor, and an emitter terminal connected to the other terminal of the fifth resistor; and

a sixth resistor (Rf) connected between a collector terminal of the third transistor and a collector terminal of the bias transistor.

2. The temperature-compensated bias circuit of claim 1 , wherein the voltage of the collector terminal of the bias transistor is determined by a voltage of the contact point between the second resistor and the third resistor.

3. The temperature-compensated bias circuit of claim 1 , wherein the voltage of the collector terminal of the bias transistor is changed according to a value of the fourth resistor.

4. A temperature-compensated bias circuit for a power amplifier comprising:

a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q 3 ) and an emitter terminal of the third transistor is connected to a first diode (D 1 );

a second diode (D 2 ) connected to the reference voltage;

a second resistor (R 1 ) connected to the second diode;

a third resistor (R 2 ) connected to the second resistor in series;

a fourth resistor (Rc) having one terminal connected to the reference voltage;

a fifth resistor (Re) having one terminal connected to ground;

a bias transistor (Q 4 ) having a base terminal connected to a contact point (VS) between the second resistor and the third resistor, a collector terminal connected to the other terminal of the fourth resistor, and an emitter terminal connected to the other terminal of the fifth resistor; and

a sixth resistor (Rf) connected between a collector terminal of the third transistor and the collector terminal of the bias transistor.

5. The temperature-compensated bias circuit of claim 4 , wherein the voltage of the collector terminal of the bias transistor is determined by a voltage of the contact point between the second resistor and the third resistor.

6. The temperature-compensated bias circuit of claim 4 , wherein the voltage of the collector terminal of the bias transistor is changed according to a value of the fourth resistor.

7. The temperature-compensated bias circuit of claim 2 , wherein the second diode is disposed between the second resistor and the contact point.

8. A temperature-compensated bias circuit for a power amplifier comprising:

a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q 3 ) and an emitter terminal of the third transistor is connected to a first diode (D 1 );

a second resistor (R 1 ) connected to the reference voltage;

a third resistor (R 2 ) connected to the second resistor in series;

a sixth resistor (Re) having one terminal connected to ground;

a bias transistor (Q 4 ) having a base terminal connected to a contact point (VS) between the second resistor and the third resistor and an emitter terminal connected to the other terminal of the sixth resistor; and

a seventh resistor (Rf) connected between a collector terminal of the third transistor (Q 3 ) and a collector terminal of the bias transistor.

9. The temperature-compensated bias circuit of claim 8 , wherein the voltage of the collector terminal of the bias transistor is determined by a voltage of the contact point between the second resistor and the third resistor.

10. A temperature-compensated bias circuit for a power amplifier comprising:

a first resistor (Rref) connected to a reference voltage is connected to a base terminal of a third transistor (Q 3 ) and an emitter terminal of the third transistor is connected to a first diode (D 1 );

a second diode (D 2 ) connected to the reference voltage;

a second resistor (R 1 ) connected to the second diode;

a third resistor (R 2 ) connected to the second resistor in series;

a sixth resistor (Re) having one terminal connected to ground;

a bias transistor (Q 4 ) having a base terminal connected to a contact point (VS) between the second resistor and the third resistor and an emitter terminal connected to the other terminal of the sixth resistor; and

a seventh resistor (Rf) connected between a collector terminal of the third transistor (Q 3 ) and a collector terminal of the bias transistor.

11. The temperature-compensated bias circuit of claim 10 , wherein the voltage of the collector terminal of the bias transistor is determined by a voltage of the contact point between the second resistor and the third resistor.

12. The temperature-compensated bias circuit of claim 10 , wherein the second diode is disposed between the second resistor and the contact point.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
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To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2005
From: JEON, MOON-SUK JEON; JUNG, SANG HWA; KIM, JUNGHYUN
To: WAVICS, INC.
Reel/Frame 016376/0681 →