IP Library Granted Patent US 7,164,316
Granted Patent B2
US 7,164,316 · App. 10/905,661 · Granted Jan 16, 2007

Series-Type Doherty Amplifier Without Hybrid Coupler

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Quick Facts
Patent No.
US 7,164,316
App. No.
10/905,661
Granted
Jan 16, 2007
Kind
B2
Abstract

Provided is a series type Doherty amplifier which includes a first power amplifier and a second power amplifier using a plurality of transformers. The first power amplifier and the second power amplifier are connected in series. The second power amplifier and a first transformer are connected in series. A first path is branched from a junction between the first power amplifier and the second power amplifier and a phase delay device and a second transformer are connected in series. An output port of the second transformer is connected to a junction of a second path of an output port of the second power amplifier. An efficiency of each power amplifier is determined by a ratio of 1:M in size of a final stage of each of the first and second power amplifiers.

Claims (35)

1. A series type Doherty amplifier comprising a first power amplifier and a second power amplifier using a plurality of transformers, wherein the first power amplifier and the second power amplifier are connected in series, the second power amplifier and a first transformer are connected in series, a first path is branched from a junction between the first power amplifier and the second power amplifier and a phase delay device and a second transformer are connected in series, an output port of the second transformer is connected to a junction of a second path of an output port of the second power amplifier, and an efficiency of each power amplifier is determined by a ratio of 1:M in size of a final stage of each of the first and second power amplifiers.

2. The series type Doherty amplifier of claim 1 , further comprising a control portion applying an external bias to each of the first and second power amplifiers according to an output power level.

3. The series type Doherty amplifier of claim 1 , wherein the phase delay device, the first transformer, and the second transformer are embodied with a passive device L or C, a micro-strip, and an active device.

4. The series type Doherty amplifier of claim 2 , wherein the phase delay device, the first transformer, and the second transformer are embodied with a passive device L or C, a micro-strip, and an active device.

5. The series type Doherty amplifier of claim 3 , wherein the phase delay device and the second transformer are embodied with an equivalent circuit.

6. The series type Doherty amplifier of claim 4 , wherein the phase delay device and the second transformer are embodied with an equivalent circuit.

7. The series type Doherty amplifier of claim 1 , wherein the first power amplifier and the second power amplifier comprise an input/output matching circuit and a bias circuit.

8. The series type Doherty amplifier of claim 3 , wherein the first power amplifier and the second power amplifier comprise an input/output matching circuit and a bias circuit.

9. The series type Doherty amplifier of claim 4 , wherein the first power amplifier and the second power amplifier comprise an input/output matching circuit and a bias circuit.

10. The series type Doherty amplifier of claim 7 , wherein each of the first power amplifier and the second power amplifier is formed of at least one stage.

11. The series type Doherty amplifier of claim 8 , wherein each of the first power amplifier and the second power amplifier is formed of at least one stage.

12. The series type Doherty amplifier of claim 9 , wherein each of the first power amplifier and the second power amplifier is formed of at least one stage.

13. The series type Doherty amplifier of claim 10 , wherein a high efficiency is maintained at a low output power as the ratio in size of the final stage of each of the first power amplifier and the second power amplifier.

14. The series type Doherty amplifier of claim 11 , wherein a high efficiency is maintained at a low output power as the ratio in size of the final stage of each of the first power amplifier and the second power amplifier.

15. The series type Doherty amplifier of claim 12 , wherein a high efficiency is maintained at a low output power as the ratio in size of the final stage of each of the first power amplifier and the second power amplifier.

16. A series type Doherty amplifier comprising N units of power amplifiers which are connected in series using a plurality of transformers, wherein a first power amplifier and a second power amplifier are connected in series, an output port of the second power amplifier is connected to a (2(N−1)−1)th transformer in series, an output port of an (N−1)th power amplifier is connected to a third transformer in series, an output port of a third transformer is connected to an N-th power amplifier, and the N-th power amplifier is connected to a first transformer in series,

wherein a first path is branched from a junction between the N-th power amplifier and the third transformer is connected to a first phase compensation portion in which a first phase delay device and a second transformer are connected in series, and an output port of the first phase compensation portion is connected to a junction between the N-th power amplifier and the first transformer,

wherein a second path branched from a junction between the (N−1)th power amplifier and the (2(N−1)−1)th transformer is connected to a second phase compensation portion in which a second phase delay device and a fourth transformer are connected in series, and an output port of the second phase compensation portion is connected to a junction between the (N−1)th power amplifier and the third transformer,

wherein a third path branched from a junction between the first power amplifier and the second power amplifier is connected to the (N−1)th phase compensation portion in which an (N−1)th phase delay device and a (2(N−1))th transformer are connected in series, and an output port of the (N−1)th phase compensation portion is connected to a junction between the second power amplifier and the (2(N−1)−1)th transformer, and

wherein a total efficiency is determined by the number of stages of the power amplifier, that is, N.

17. The series type Doherty amplifier of claim 16 , further comprising a control portion applying an external bias to each of the N units of the power amplifiers according to an output power level.

18. The series type Doherty amplifier of claim 16 , wherein the first phase delay device, the second phase delay device, the (N−1)th phase delay device, the first transformer, the second transformer, the third transformer, the fourth transformer, the (2(N−1)−1)th transformer, and the 2(N−1)th transformer are embodied with a passive device L or C, a micro-strip, and an active device.

19. The series type Doherty amplifier of claim 17 , wherein the first phase delay device, the second phase delay device, the (N−1)th phase delay device, the first transformer, the second transformer, the third transformer, the fourth transformer, the (2(N−1)−1)th transformer, and the 2(N−1)th transformer are embodied with a passive device L or C, a micro-strip, and an active device.

20. The series type Doherty amplifier of claim 18 , wherein the first phase delay device and the second transformer are embodied with an equivalent circuit.

21. The series type Doherty amplifier of claim 19 , wherein the first phase delay device and the second transformer are embodied with an equivalent circuit.

22. The series type Doherty amplifier of claim 18 , wherein the second phase delay device and the fourth transformer are embodied with an equivalent circuit.

23. The series type Doherty amplifier of claim 19 , wherein the second phase delay device and the fourth transformer are embodied with an equivalent circuit.

24. The series type Doherty amplifier of claim 18 , wherein the (N−1)th phase delay device and the 2(N−1)th transformer are embodied with an equivalent circuit.

25. The series type Doherty amplifier of claim 19 , wherein the (N−1)th phase delay device and the 2(N−1)th transformer are embodied with an equivalent circuit.

26. The series type Doherty amplifier of claim 16 , wherein the first through N-th power amplifiers comprise an input/output matching circuit and a bias circuit.

27. The series type Doherty amplifier of claim 17 , wherein the first through N-th power amplifiers comprise an input/output matching circuit and a bias circuit.

28. The series type Doherty amplifier of claim 26 , wherein each of the first through N-th power amplifiers is formed of at least one stage.

29. The series type Doherty amplifier of claim 27 , wherein each of the first through N-th power amplifiers is formed of at least one stage.

30. The series type Doherty amplifier of claim 16 , wherein an N times high efficiency is maintained in a total output power by depending on the number of stages of the power amplifier, that is, N.

31. The series type Doherty amplifier of claim 17 , wherein an N times high efficiency is maintained in a total output power by depending on the number of stages of the power amplifier, that is, N.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2005
From: KIM, JUNGHYUN; JUNG, JOO-MING
To: WAVICS, INC.
Reel/Frame 016376/0914 →
Continuity (1)
Related Publication 20060109053A1 · May 25, 2006