IP Library › Granted Patent US 7,135,769
Granted Patent B2
US 7,135,769 · App. 10/907,327 · Granted Nov 14, 2006

Semiconductor packages and methods of manufacturing thereof

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 7,135,769
App. No.
10/907,327
Granted
Nov 14, 2006
Kind
B2
Abstract

Described are semiconductor package devices with improved reliability and methods of manufacturing thereof. In one embodiment, a package device is disclosed that includes a chip having an active surface and a coupling surface opposite the active surface, where the chip has one or more integrated circuits and bumps. The device also includes a thermal spreader thermally coupled to the coupling surface of the chip for dissipating heat generated by the chip, and a thermal interface material located between the thermal spreader and the coupling surface of the chip for improving the heat dissipation. In addition, the device also includes a boundary material located between the thermal spreader and the coupling surface of the chip, where the boundary material is configured to surround a perimeter of the thermal interface material to maintain the thermal interface material between the thermal spreader and the coupling surface of the chip.

Claims (14)

1. A semiconductor package, comprising:

a chip having an active surface and a coupling surface opposite the active surface, the chip having one or more integrated circuits and bumps;

a thermal spreader thermally coupled to the coupling surface of the chip;

a thermal interface material located between the thermal spreader and the coupling surface of the chip;

a boundary material located between the thermal spreader and the coupling surface of the chip, the boundary material surrounding a perimeter of the thermal interface material to maintain the thermal interface material between the thermal spreader and the coupling surface of the chip; and

an adhesive material located between the boundary material and the coupling surface of the chip.

2. A package according to claim 1 , further comprising a substrate having an upper surface and a lower surface opposite the upper surface, wherein the active surface of the chip is flip-chip bonded to the upper surface of the substrate using electrical connections extending between the substrate and the chip.

3. A package according to claim 1 , wherein the boundary material is a polymer material.

4. A package according to claim 3 , wherein the polymer material is selected from the group consisting of polyester-based material and polytetrafluoroethlene (PTFE).

5. A package according to claim 1 , wherein the perimeter of the thermal interface material maintains a shape selected from the group consisting of a rectangle, a square, and a circle.

6. A package according to claim 1 , wherein the thermal interface material is selected from the group consisting of thermal grease, air, and thermal gel.

7. A package according to claim 1 , wherein the thermal spreader comprises a recess region configured to receive at least a portion of the boundary material.

8. A package according to claim 1 , wherein the thermal interface material comprises a thickness less than a thickness of the boundary material.

9. A package according to claim 1 , wherein the boundary material is in moveable contact with the thermal spreader.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2005
From: NI, CHING-YU; YUAN, TSORNG-DIH; PAN, HSIN-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 015837/0209 →
Continuity (1)
Related Publication 20060220225A1 · Oct 5, 2006