IP Library › Granted Patent US 7,436,747
Granted Patent B2
US 7,436,747 · App. 10/908,823 · Granted Oct 14, 2008

Detector and method for detecting synchronization signals in disc system

Assignee: Realtek Semiconductor Corp.
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Quick Facts
Patent No.
US 7,436,747
App. No.
10/908,823
Granted
Oct 14, 2008
Kind
B2
Abstract

A detector and a method for detecting synchronization signals in a disc system are disclosed. The method includes sampling a disc signal with a sampling clock to generate a plurality of sampled data, comparing the plurality of sampled data with a predetermined synchronization pattern to generate a comparison result, performing the above-mentioned comparing step after a predetermined time interval, and outputting a synchronization signal and adjusting the time for outputting the synchronization signal according to the comparison results.

Claims (27)

1. A method for detecting synchronization signals in a disc system, comprising:

sampling a disc signal with a sampling clock to generate a plurality of sampled data;

comparing the sampled data with a predetermined synchronization pattern to determine a time of a first synchronization pattern occurring in the sampled data;

determining a time of a second synchronization pattern occurring in the sampled data according to a predetermined interval after the time of the first synchronization pattern;

comparing the plurality of sampled data with the predetermined synchronization pattern within a range around the time of the second synchronization pattern to thereby generate a plurality of respective computation values;

determining whether the time of the second synchronization pattern is correct according to the computation values; and

predicting a time of a third synchronization pattern according to the predetermined interval when the time of the second synchronization pattern is correct, and according to an adjusted interval generated by the predetermined interval and the computation values when the time of the second synchronization pattern is incorrect.

2. The method of claim 1 , wherein the predetermined synchronization pattern comprises fourteen successive logical values “1”.

3. The method of claim 1 wherein the predetermined interval is substantially equal to the time needed for generating the sampled data corresponding to a frame.

4. The method of claim 1 , wherein the predetermined time interval corresponds to 1488 cycles of the sampling clock.

5. The method of claim 3 , wherein the adjusted interval is substantially equal to the time needed for generating the sampled data corresponding to the frame being adjusted by n sampling clock cycles, n being an integer associated with the computation values.

6. The method of claim 1 , wherein the step of generating the computation values comprises calculating a computation value for each of the sampling clocks within the range around the time of the second synchronization pattern, each computation value representing a similarity between the sampled data and the predetermined synchronization pattern.

7. The method of claim 6 , further comprising:

determining an offset of a maximum computation value from a center position of the computation values, the maximum computation value corresponding to a highest similarity between the sampled data and the predetermined synchronization pattern, and the center position corresponding to a computation value calculated at a middle sampling clock of the range; and

adjusting the predetermined interval to form the adjusted interval by a number of sampling clocks being equal to the offset.

8. The method of claim 1 , wherein the disc is an optical disc.

9. A detector utilized in an optical storage device, comprising:

a sampling module for sampling a disc signal with a sampling clock to generate a plurality of sampled data;

a comparing module electrically coupled to the sampling module for comparing the sampled data with a predetermined synchronization pattern to determine a time of a first synchronization pattern occurring in the sampled data, determining a time of a second synchronization pattern occurring in the sampled data according to a predetermined interval after the time of the first synchronization pattern, and for comparing the plurality of sampled data with the predetermined synchronization pattern within a range around a time of a second synchronization pattern occurring in the sampled data to thereby generate a plurality of respective computation values; and

an adjusting module electrically coupled to the comparing module for predicting a time of a third synchronization pattern according to the predetermined interval when the time of the second synchronization pattern is correct, and according to an adjusted interval generated by the predetermined interval and the computation values when the time of the second synchronization pattern is incorrect.

10. The detector of claim 9 , wherein the predetermined synchronization pattern comprises fourteen successive logical values “1”.

11. The detector of claim 9 wherein the predetermined interval is substantially equal to the time needed for generating the sampled data corresponding to a frame.

12. The detector of claim 9 , wherein the predetermined time interval corresponds to 1488 cycles of the sampling clock.

13. The detector of claim 11 , wherein the adjusted interval is substantially equal to the time needed for generating the sampled data corresponding to the frame being adjusted by n clock cycles, n being an integer associated with the computation values.

14. The detector of claim 9 , wherein the comparing module is further for calculating a computation value for each of the sampling clocks within the range around the time of the second synchronization pattern, each computation value representing a similarity between the sampled data and the predetermined synchronization pattern.

15. The detector of claim 14 , wherein the adjusting module is further for determining an offset of a maximum computation value from a center position of the computation values, the maximum computation value corresponding to a highest similarity between the sampled data and the predetermined synchronization pattern, and the center position corresponding to a computation value calculated at a middle sampling clock of the range; and for adjusting the predetermined interval to form the adjusted interval by a number of sampling clocks being equal to the offset.

16. The detector of claim 9 , wherein the disc is an optical disc.

Assignments (2)
CHANGE OF THE ADDRESS OF THE ASSIGNEE Recorded Sep 4, 2008
From: REALTEK SEMICONDUCTOR CORP.
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 021477/0570 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2005
From: YEN, KUANG-YU
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 016068/0270 →
Priority Claims (1)
TW 93115489 A · May 31, 2004 · national
Continuity (1)
Related Publication 20050265198A1 · Dec 1, 2005