MOS transistor and fabrication method thereof
View Patent ↗A MOS transistor and a method for fabricating the MOS transistor. The present invention enables implementation of a stable semiconductor device that is capable of protecting against leakage current generation by improving the “LDD effect” and securing a large process margin by adjusting an “off” current. The method for fabricating a MOS transistor includes placing or arranging an epitaxial layer between a silicon wafer and a gate electrode, and forming three impurity regions, including a very low concentration impurity region, and a low concentration impurity region and a high concentration impurity region (source and drain region).
1. A method for fabricating a MOS transistor comprising the steps of:
a) forming low concentration impurity regions in a semiconductor substrate;
b) sequentially forming an epitaxial layer and gate oxide layer on the semiconductor substrate;
c) forming a gate on said gate oxide layer, between the low concentration impurity regions, with a CD narrower than that between the low concentration impurity regions;
d) forming very low concentration impurity regions in the epitaxial layer using the gate as a mask;
e) forming spacers adjacent to the gate and the epitaxial layer; and
f) forming source/drain regions in the semiconductor substrate using the spacer as a mask.
2. The method of claim 1 , wherein the step of forming low concentration impurity regions includes:
a-1) forming a pattern on the semiconductor substrate;
a-2) injecting an impurity into the semiconductor substrate in low concentration using the pattern as a mask; and
a-3) removing the pattern.
3. The method of claim 2 , wherein the pattern is formed from a photoresist.
4. The method of claim 1 , wherein the step of sequentially forming the epitaxial layer and the gate oxide layer includes:
b-1) forming a sacrificial layer on the semiconductor substrate;
b-2) forming a window in the sacrificial layer, exposing the semiconductor substrate between the low concentration impurity regions; and
b-3) sequentially forming an epitaxial layer on the exposed semiconductor substrate and a gate oxide layer on the epitaxial layer.
5. The method of claim 4 , further comprising removing the sacrificial layer after forming the very low concentration impurity regions.
6. The method of claim 4 , wherein forming said window comprises selectively etching the sacrificial layer.
7. The method of claim 4 , wherein the sacrificial layer comprises a nitride layer.
8. The method of claim 4 , wherein the nitride layer has a thickness in the range of 100–1000 Å.
9. The method of claim 3 , wherein the epitaxial layer has a thickness in the range of 100–500 Å.
10. The method of claim 1 , wherein the step of forming the very low concentration impurity region comprises injecting or implanting impurity ions into said epitaxial layer at a very low concentration.
11. The method of claim 10 , further including forming a protection layer on the gate before injecting or implanting said impurity ions into said epitaxial layer.
12. The method of claim 1 , wherein the step of forming the source/drain regions comprises injecting or implanting impurity ions into said semiconductor substrate at a concentration higher than that of said low concentration impurity regions.
13. The method of claim 1 , further comprising a step of forming a cap oxide layer on an entire surface of the semiconductor substrate including the gate before forming the spacer.