Ternary and higher multi-value digital scramblers/descramblers
Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
1. A method of scrambling a first ternary signal with a scrambler, each ternary signal being able to assume on of three states and the scrambler having a first scrambling ternary logic device that implements a ternary logic function, sc, the first scrambling ternary logic device having a first input enabled to receive the first ternary signal and a second input enabled to receive a second ternary signal and an output enabled to provide a third ternary signal and a scrambling logic circuit having an input and an output enabled to provide the second ternary signal, comprising:
inputting the ternary signal on the first input of the first scrambling ternary logic device and providing the second ternary signal from the output of the scrambling logic circuit to the second input of the first scrambling ternary logic device;
inputting the third ternary signal provided on the output of the first scrambling ternary logic device to the input of the scrambling logic circuit;
wherein a state of the first ternary signal on the first input of the first scrambling ternary device may be represented by A, a state of the second ternary signal on the second input of the first scrambling ternary device may be represented by B and a state of the third ternary signal provided on the output of the first scrambling ternary device may be represented by C, and the ternary logic function, sc, satisfies the following equations for all possible combinations of A and B:
A sc B=C;
C sc B=A; and
A sc C=B; and
whereby the output of the first scrambling ternary logic device provides a scrambled version of the ternary signal.
2. The method as claimed in claim 1 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
0
2
1
1
2
1
0
2
1
0
2.
3. The method as claimed in claim 1 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
1
0
2
1
0
2
1
2
2
1
0.
4. The method as claimed in claim 1 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
2
1
0
1
1
0
2
2
0
2
1.
5. The method as claimed in claim 1 , wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device.
6. The method as claimed in claim 5 , wherein n is equal to five and the outputs from the third and fifth elements are input to the second ternary logic device.
7. The method as claimed in claim 1 , wherein the scrambled version of the ternary signal is descrambled with a descrambling device having a first descrambling ternary logic device and a descrambling logic circuit, the first descrambling ternary logic device implementing the ternary logic function, sc, the method comprising:
inputting the scrambled version of the ternary signal to the first descrambling ternary logic device and to the descrambling logic circuit;
inputting an output from the descrambling logic circuit to the first descrambling ternary logic device; and
outputting a descrambled ternary signal on an output of the first descrambling ternary logic device.
8. The method as claimed in claim 7 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
0
2
1
1
2
1
0
2
1
0
2.
9. The method as claimed in claim 7 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
1
0
2
1
0
2
1
2
2
1
0.
10. The method as claimed in claim 7 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
2
1
0
1
1
0
2
2
0
2
1.
11. The method as claimed in claim 7 wherein:
the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device, and
the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling ternary logic device, and wherein the output from the second descrambling ternary logic device is provided to an input of the first descrambling ternary logic device and the scrambled version of the ternary signal is input to the descrambling n-length shift register.
12. Apparatus for scrambling a first ternary signal, each ternary signal being able to assume one of three states, comprising:
a first scrambling ternary logic device that implements a ternary logic function, sc, the first scrambling ternary logic device having a first input enabled to receive the first ternary signal and a second input enabled to receive a second ternary signal and an output enabled to provide a third ternary signal;
a scrambling logic circuit having an input and an output;
wherein the first ternary signal is input to the first input of the first scrambling ternary logic device, the second ternary signal which is provided on the output of the scrambling logic circuit is input to the second input of the first scrambling ternary logic device and the third ternary signal which is provided on the output of the first scrambling ternary logic devices is provided to the input of the scrambling logic circuit, wherein a state of the first ternary signal on the first input of the first scrambling ternary device may be represented by A, a state of the second ternary signal on the second input of the first scrambling ternary device may be represented by B and a state of the third ternary signal provided on the output of the first scrambling ternary device may be represented by C, and the ternary logic function, sc, satisfies the following equations for all possible combinations of A and B:
(1) A sc B=C;
(2) C sc B=A; and
(3) A sc C=B; and
whereby a scrambled ternary signal is provided on the output of the first scrambling ternary logic device.
13. The apparatus as claimed in claim 12 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
0
2
1
1
2
1
0
2
1
0
2.
14. The apparatus as claimed in claim 12 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
1
0
2
1
0
2
1
2
2
1
0.
15. The apparatus as claimed in claim 12 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
2
1
0
1
1
0
2
2
0
2
1.
16. The apparatus as claimed in claim 12 , wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device.
17. The apparatus as claimed in claim 12 , further including a descrambler for descrambling the scrambled ternary signal, comprising:
a first descrambling ternary logic device that implements the ternary logic function, sc, the first descrambling ternary logic device having a first and second input and an output;
a descrambling logic circuit having an input and an output;
wherein the scrambled ternary signal is input to the first input of the first descrambling ternary logic device and to the input of the descrambling logic device and the output of the descrambling logic device is input to the second input of the first descrambling ternary logic device;
whereby a descrambled ternary signal is provided on the output of the first descrambling ternary logic device.
18. The apparatus as claimed in claim 17 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
0
2
1
1
2
1
0
2
1
0
2.
19. The apparatus as claimed in claim 17 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
1
0
2
1
0
2
1
2
2
1
0.
20. The apparatus as claimed in claim 17 , wherein the ternary logic function, sc, is defined by the following truth table:
In2
In1
0
1
2
0
2
1
0
1
1
0
2
2
0
2
1.
21. The apparatus as claimed in claim 17 wherein:
the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling ternary logic device, and wherein the output from the first scrambling ternary logic device is provided to an input of the n-length shift register and an output of the second scrambling ternary logic device is provided to an input of the first scrambling ternary logic device, and
the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling ternary logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling ternary logic device, and wherein the output from the second descrambling ternary logic device is provided to an input of the first descrambling ternary logic device and the scrambled version of the ternary signal is input to the descrambling n-length shift register.
22. A method of scrambling a first multi-value signal, each multi-value signal being able to assume one of x states, wherein x is greater than or equal to 4, with a scrambler, the scrambler having a first scrambling multi-value logic device that implements a multi-value-logic function, fc, with a first input enabled to receive the first multi-value signal and a second input enabled to receive a second multi-value signal and an output enabled to provide a third multi-value signal and a scrambling logic circuit having an input and an output, comprising:
inputting the first multi-value signal on the first input of the first scrambling multi-value logic device and inputting the second multi-value signal that is provided on the output of the scrambling logic circuit on the second input of the first scrambling multi-value logic device;
inputting the third multi-value signal that is provided on the output of the first scrambling multi-value logic device on the input of the scrambling logic circuit; wherein a state of the first multi-value signal on the first input of the first scrambling multi-value device may be represented by A, a state of the second multi-value signal on the second input of the first scrambling multi-value device may be represented by B and a state of the third multi-value signal provided on the output of the first scrambling multi-value device may be represented by C, and the multi-value logic function, fc, satisfies the following equations for all possible combinations of A and B:
(1) A fc B=C;
(2) C fc B=A; and
(3) A fc C=B; and
whereby the output of the first scrambling multi-value logic device provides a scrambled version of the multi-value signal.
23. The method as claimed in claim 22 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
0
3
2
1
1
3
2
1
0
2
2
1
0
3
3
1
0
3
2.
24. The method as claimed in claim 22 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
1
0
3
2
1
0
3
2
1
2
3
2
1
0
3
2
1
0
3.
25. The method as claimed in claim 22 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
2
1
0
3
1
1
0
3
2
2
0
3
2
1
3
3
2
1
0.
26. The method as claimed in claim 22 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
3
2
1
0
1
2
1
0
3
2
1
0
3
2
3
0
3
2
1.
27. The method as claimed in claim 22 , wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device.
28. The method as claimed in claim 22 , wherein n is equal to five and the outputs from the third and fifth shift registers are input to the second multi-value logic device.
29. The method as claimed in claim 22 , wherein the scrambled version of the multi-value signal is descrambled with a descrambling device having a first descrambling multi-value logic device and a descrambling logic circuit, the first descrambling multi-value logic device implementing the multi-value logic function, fc, the method comprising:
inputting the scrambled version of the multi-value signal to the first descrambling multi-value logic device and to the descrambling logic circuit;
inputting an output from the descrambling logic circuit to the first descrambling multi-value logic device; and
outputting a descrambled multi-value signal on an output of the first descrambling multi-value logic device.
30. The method as claimed in claim 29 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
0
3
2
1
1
3
2
1
0
2
2
1
0
3
3
1
0
3
2.
31. The method as claimed in claim 29 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
1
0
3
2
1
0
3
2
1
2
3
2
1
0
3
2
1
0
3.
32. The method as claimed in claim 29 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
2
1
0
3
1
1
0
3
2
2
0
3
2
1
3
3
2
1
0.
33. The method as claimed in claim 29 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
3
2
1
0
1
2
1
0
3
2
1
0
3
2
3
0
3
2
1.
34. The method as claimed in claim 29 wherein:
the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device, and
the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling multi-value logic device, and wherein the output from the second descrambling multi-value logic device is provided to an input of the first descrambling multi-value logic device and the scrambled version of the multi-value signal is input to the descrambling n-length shift register.
35. Apparatus for scrambling a first multi-value signal, each multi-value signal able to assume one of x states, wherein x is greater than or equal to 4, comprising:
a first scrambling multi-value logic device that implements a multi-value logic function, fc, the first multi-value logic device having a first and second input and an output;
a scrambling logic circuit having an input and an output;
wherein the multi-value signal is input to the first input of the first scrambling multi-value logic device, a second multi-value signal that is provided on the output of the scrambling logic circuit is input to the second input of the first scrambling multi-value logic device and a third multi-value signal that is provided on the output of the first scrambling multi-value logic device is input to the input of the scrambling logic circuit, a state of the first multi-value signal on the first input of the first scrambling multi-value device may be represented by A, a state of the second multi-value signal on the second input of the first scrambling multi-value device may be represented by B and a state of the third multi-value signal provided on the output of the first scrambling multi-value device may be represented by C, and the multi-value logic function, fc, satisfies the following equations for all possible combinations of A and B:
(1) A fc B=C;
(2) C fc B=A; and
(3) A fc C=B; and
whereby a scrambled multi-value signal is provided on the output of the first scrambling multi-value logic device.
36. The apparatus as claimed in claim 35 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
0
3
2
1
1
3
2
1
0
2
2
1
0
3
3
1
0
3
2.
37. The apparatus as claimed in claim 35 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
1
0
3
2
1
0
3
2
1
2
3
2
1
0
3
2
1
0
3.
38. The apparatus as claimed in claim 35 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
2
1
0
3
1
1
0
3
2
2
0
3
2
1
3
3
2
1
0.
39. The apparatus as claimed in claim 35 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
3
2
1
0
1
2
1
0
3
2
1
0
3
2
3
0
3
2
1.
40. The apparatus as claimed in claim 35 , wherein the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device.
41. The apparatus as claimed in claim 35 further including a descrambler for descrambling the scrambled multi-value signal, comprising:
a first descrambling multi-value logic device that implements the multi-value logic function, fc, the first descrambling multi-value logic device having a first and second input and an output;
a descrambling logic circuit having an input and an output;
wherein the scrambled multi-value signal is input to the first input of the first descrambling multi-value logic device and to the input of the descrambling logic circuit and the output of the descrambling logic circuit is input to the second input of the first descrambling multi-value logic device;
whereby a descrambled multi-value signal is provided on the output of the first descrambling multi-value logic device.
42. The apparatus as claimed in claim 41 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
0
3
2
1
1
3
2
1
0
2
2
1
0
3
3
1
0
3
2.
43. The apparatus as claimed in claim 41 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
1
0
3
2
1
0
3
2
1
2
3
2
1
0
3
2
1
0
3.
44. The apparatus as claimed in claim 41 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
2
1
0
3
1
1
0
3
2
2
0
3
2
1
3
3
2
1
0.
45. The apparatus as claimed in claim 41 , wherein x is equal to 4 and the multi-value logic function, fc, is defined by the following truth table:
In2
In1
0
1
2
3
0
3
2
1
0
1
2
1
0
3
2
1
0
3
2
3
0
3
2
1.
46. The apparatus as claimed in claim 41 wherein:
the scrambling logic circuit includes a scrambling n-length shift register having n elements and a second scrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second scrambling multi-value logic device, and wherein the output from the first scrambling multi-value logic device is provided to an input of the n-length shift register and an output of the second scrambling multi-value logic device is provided to an input of the first scrambling multi-value logic device, and
the descrambling logic circuit includes a descrambling n-length shift register having n elements and a second descrambling multi-value logic device, the scrambling n-length shift register having outputs from two of the n elements that are provided to two inputs of the second descrambling multi-value logic device, and wherein the output from the second descrambling multi-value logic device is provided to an input of the first descrambling multi-value logic device and the scrambled version of the multi-value signal is input to the descrambling n-length shift register.