IP Library Assignment 072838/0394
Patent Assignment
Reel/Frame 072838/0394

Assignment of Assignor's Interest

Recorded: 2025-11-08 Pages: 8
Assignor
TERNARYLOGIC LLC
Executed: 2025-11-08
Assignee
LABLANS, PETER, MR.
8 HARVEY COURT, MORRISTOWN, NEW JERSEY, 07960-6225
Covered Properties (41)
Ternary and Higher Multi-Value Digital Scramblers/Descramblers
Patent: 7,505,589 →
Application: 10/912,954 →
Publication: US 2005/0053240
Ternary and Multi-Value Digital Signal Scramblers, Descramblers and Sequence Generators
Patent: 7,643,632 →
Application: 10/935,960 →
Publication: US 2005/0185796
Ternary and Higher Multi-Value Digital Scramblers/Descramblers
Patent: 7,002,490 →
Application: 10/936,181 →
Publication: US 2005/0084111
Single and Composite Binary and Multi-Valued Logic Functions from Gates and Inverters
Patent: 7,218,144 →
Application: 11/000,218 →
Publication: US 2005/0194993
Multi-Value Digital Calculating Circuits, Including Multipliers
Patent: 7,562,106 →
Application: 11/018,956 →
Publication: US 2006/0031278
Multi-Valued Scrambling and Descrambling of Digital Data on Optical Disks and Other Storage Media
Patent: 7,725,779 →
Application: 11/042,645 →
Publication: US 2006/0164883
Generation and Detection of Non-Binary Digital Sequences
Patent: 7,580,472 →
Application: 11/065,836 →
Publication: US 2005/0184888
Multi-Valued Digital Information Retaining Elements and Memory Devices
Patent: 7,397,690 →
Application: 11/139,835 →
Publication: US 2005/0278661
Sequence Detection by Multi-Valued Coding and Creation of Multi-Code Sequences
Patent: 7,064,684 →
Application: 11/141,336 →
Publication: US 2005/0265463
Sequence Detection by Multi-Valued Coding and Creation of Multi-Code Sequences
Patent: 7,277,030 →
Application: 11/407,496 →
Publication: US 2006/0187092
The Creation and Detection of Binary and Non-Binary Pseudo-Noise Sequences Not Using LFSR Circuits
Application: 11/427,498 →
Publication: US 2007/0005673
Binary Digital Latches Not Using Only Nand or nor Circuits
Patent: 7,365,576 →
Application: 11/448,404 →
Publication: US 2006/0282607
Encipherment of Digital Sequences by Reversible Transposition Methods
Patent: 7,930,331 →
Application: 11/534,777 →
Publication: US 2007/0071068
Generation and Self-Synchronizing Detection of Sequences Using Addressable Memories
Application: 11/534,837 →
Publication: US 2007/0088997
Scrambling and Self-Synchronizing Descrambling Methods for Binary and Non-Binary Digital Signals Not Using Lfsrs
Application: 11/555,730 →
Publication: US 2007/0098160
Error Correcting Decoding for Convolutional and Recursive Systematic Convolutional Encoded Sequences
Patent: 7,877,670 →
Application: 11/566,725 →
Publication: US 2007/0226594
Multi-Valued Check Symbol Calculation in Error Detection and Correction
Patent: 7,865,807 →
Application: 11/680,719 →
Publication: US 2007/0258516
Single and Composite Binary and Multi-Valued Logic Functions from Gates and Inverters
Patent: 7,355,444 →
Application: 11/686,542 →
Publication: US 2007/0152710
Binary and N-Valued Lfsr and Lfcsr Based Scramblers, Descramblers, Sequence Generators and Detectors in Galois Configuration
Patent: 7,487,194 →
Application: 11/696,261 →
Publication: US 2007/0239812
Symbol Reconstruction in Reed-Solomon Codes
Patent: 8,103,943 →
Application: 11/743,893 →
Publication: US 2008/0040650
Error Correction in Multi-Valued (p,k) Codes
Patent: 9,203,436 →
Application: 11/775,963 →
Publication: US 2008/0016432
Symbol Error Correction by Error Detection and Logic Based Symbol Reconstruction
Patent: 8,046,661 →
Application: 11/969,560 →
Publication: US 2008/0104479
Multi-State Latches from N-State Reversible Inverters
Patent: 7,656,196 →
Application: 12/061,286 →
Publication: US 2008/0180987
Methods and Systems for Modifying the Statistical Distribution of Symbols in a Coded Message
Patent: 7,659,839 →
Application: 12/188,261 →
Publication: US 2009/0045988
Implementing Logic Functions with Non-Magnitude Based Physical Phenomena
Patent: 7,696,785 →
Application: 12/339,419 →
Publication: US 2009/0128190
Multi-State Symbol Error Correction in Matrix Based Codes
Patent: 8,832,523 →
Application: 12/400,900 →
Publication: US 2009/0172501
Multi-Value Digital Calculating Circuits, Including Multipliers
Patent: 8,209,370 →
Application: 12/472,731 →
Publication: US 2009/0234900
Generation and Detection of Non-Binary Digital Sequences
Patent: 8,374,289 →
Application: 12/502,410 →
Publication: US 2009/0285326
Multi-State Latches from N-State Reversible Inverters
Patent: 7,782,089 →
Application: 12/635,307 →
Publication: US 2010/0085802
Implementing Logic Functions with Non-Magnitude Based Physical Phenomena
Application: 12/710,809 →
Publication: US 2010/0164548
Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration
Application: 12/774,092 →
Publication: US 2010/0299579
Data Encryption and Decryption with a Key by an N-State Inverter Modified Switching Function
Patent: 8,149,143 →
Application: 13/083,763 →
Publication: US 2011/0182423
Methods and Systems for Rapid Error Correction by Forward and Reverse Determination of Coding States
Patent: 8,645,803 →
Application: 13/103,300 →
Publication: US 2011/0276854
Methods and Systems for Rapid Error Correction of Reed-Solomon Codes
Patent: 8,201,060 →
Application: 13/103,309 →
Publication: US 2011/0214038
Apparatus for Unconventional Non-Linear Feedback Shift Registers (NLFSRs)
Application: 15/001,157 →
Publication: US 2016/0211971
Ternary and higher value scramblers/descramblers in digital communication
Application: 60/501,335 →
Ternary and multi-value digital signal scramblers, descramblers and sequence generators
Application: 60/547,683 →
Multi-Valued Digital Signal Scramblers, Descramblers and Sequence Detectors in Implementation with Functions Over Gf(N)
Application: 60/943,682 →
Rapid Error Correction by Forward and Reverse Determination of Coding States
Application: 61/332,974 →
Method and Apparatus for Rapid Synchronization in Linear Feedback Shift Register Related N-state Symbol Sequences
Application: 61/350,247 →
Methods and Systems for Determining Characteristics of a Sequence of n-State Symbols
Application: 61/674,932 →
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Sep 7, 2004
From: LABLANS, PETER
To: TERNARYLOGIC, LLC
Reel/Frame 015761/0014 →
Assignment of Assignor's Interest Oct 27, 2004
From: LABLANS, PETER
To: TERNARYLOGIC, LLC
Reel/Frame 015924/0120 →
Assignment of Assignor's Interest Oct 27, 2004
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 015924/0155 →
Assignment of Assignor's Interest Mar 14, 2005
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 016352/0635 →
Assignment of Assignor's Interest Aug 30, 2006
From: LABLANS, PETER
To: TERNARYLOGIC, LLC
Reel/Frame 018197/0437 →
Assignment of Assignor's Interest Sep 6, 2006
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 018231/0569 →
Assignment of Assignor's Interest Sep 6, 2006
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 018231/0572 →
Assignment of Assignor's Interest Sep 26, 2006
From: LABLANS, PETER
To: TERNARYLOGIC, LLC
Reel/Frame 018300/0994 →
Assignment of Assignor's Interest Sep 27, 2006
From: LABLANS, P
To: TERNARYLOGIC, LLC
Reel/Frame 018310/0328 →
Assignment of Assignor's Interest Nov 2, 2006
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 018472/0371 →
Assignment of Assignor's Interest Mar 15, 2007
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 019015/0794 →
Assignment of Assignor's Interest Mar 19, 2007
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 019027/0624 →
Assignment of Assignor's Interest May 21, 2007
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 019319/0186 →
Assignment of Assignor's Interest Mar 10, 2008
From: LABLANS, PETER
To: TERNARYLOGIC, LLC
Reel/Frame 020620/0624 →
Corrective Assignment to Correct the Assignee Name (Without a Comma) Previously Recorded on Reel 020620 Frame 0624. Assignor(S) Hereby Confirms the Assignment. Mar 10, 2008
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 020622/0335 →
Assignment of Assignor's Interest Apr 3, 2008
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 020748/0138 →
Assignment of Assignor's Interest Apr 21, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022570/0278 →
Assignment of Assignor's Interest May 28, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022744/0100 →
Corrective Assignment to Correct the Assignee Name Should Be Changed to Read Ternarylogic Llc (No Comma) Previously Recorded on Reel 018300 Frame 0994. Assignor(S) Hereby Confirms the Assignee Name Should Read Ternarylogic Llc (No Comma). Jun 5, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022788/0156 →
Corrective Assignment to Correct the Assignee Name from Ternarylogic, Llc to Read Ternarylogic Llc (No Comma) Previously Recorded on Reel 015924 Frame 0120. Assignor(S) Hereby Confirms the Assignee Name Should Be Ternarylogic Llc (No Comma). Jun 5, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022789/0051 →
Corrective Assignment to Correct the Assignee Name to Read Ternarylogic Llc (No Comma) Previously Recorded on Reel 015761 Frame 0014. Assignor(S) Hereby Confirms the Assignee Name Should Read Ternarylogic Llc (No Comma). Jun 8, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022783/0897 →
Corrective Electronic Assignment Cover Sheet Jun 10, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022806/0480 →
Corrective Assignment to Correct the Receiving Party to Read Ternarylogic Llc (No Comma) Previously Recorded on Reel 018197 Frame 0437. Assignor(S) Hereby Confirms the Receiving Party Should Read Ternarylogic Llc (No Comma). Jun 18, 2009
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 022841/0980 →
Assignment of Assignor's Interest Nov 30, 2010
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 025430/0232 →
Assignment of Assignor's Interest Sep 20, 2011
From: LABLANS, PETER
To: TERNARYLOGIC LLC
Reel/Frame 026932/0536 →