Ternary and multi-value digital signal scramblers, descramblers and sequence generators
Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.
1. A generator of one or more signals representing one or more n-valued symbols with n>2 and n being an integer, comprising:
an n-valued Linear Feedback Shift Register (LFSR) having at least one device implementing an n-valued non-commutative reversible logic function, the at least one n-valued non-commutative reversible logic function having two inputs and an output; and
an output of the n-valued LFSR enabled to provide the one or more signals representing the one or more n-valued symbols.
2. The generator as claimed in claim 1 , wherein the one or more n-valued symbols form a pseudo-random sequence of n-valued symbols.
3. The generator as claimed in claim 1 , wherein every multiplier is a multiplier 1.
4. A method for generating one or more signals representing one or more n-valued symbols with n>2 and n being an integer, comprising:
applying an n-valued Linear Feedback Shift Register (LFSR) having one or more devices each device representing an n-valued reversible logic function, each n-valued reversible logic function having two inputs and an output, and at least one n-valued reversible logic function being non-commutative; and
providing the one or more signals representing one or more n-valued symbols on an output.
5. The method as claimed in claim 4 , wherein every multiplier is a multiplier 1.
6. A method for scrambling of signals representing p n valued symbols with n>2 and p>2 and n and p being integers by a scrambler into signals representing p n-valued scrambled symbols, comprising:
applying an n-valued Linear Feedback Shift Register (LFSR), having:
one or more devices, each device implementing an n-valued reversible logic functions, each device having two inputs and an output, and at least one n-valued reversible logic function not being a modulo-n adder; and
an n-valued shift register with an input, the shift register having q shift register elements with q<p and q being an integer;
inputting the signals representing the p n-valued symbols on a first input of a scrambling device implementing a reversible n-valued logic function, the scrambling device having a first and a second input and an output, wherein:
the second input of the scrambling device is connected to the output of one of the one or more devices implementing an n-valued reversible function;
the output of the scrambling device is connected to the input of the n-valued shift register; and
the output of the scrambling device is enabled to provide the signals representing p n-valued scrambled symbols; and
associating the scrambler with a corresponding descrambler which can recover the p n-valued symbols from the p n-valued scrambled symbols.
7. A method for descrambling with a descrambler a plurality of signals representing p n-valued scrambled symbols with n>2 and p>2 and n and p being integers, comprising: Applying an n-valued Linear Feedback Shift Register (LFSR), having: one or more devices, each device implementing an n-valued reversible logic function, each device having to inputs and an output, and at least one n-valued reversible logic function not being a modulo-n adder; and an n-valued shift register with an input, the input being enabled to receive the plurality of signals representing the p n valued scrambled symbols; and inputting the plurality of signals representing the p n-valued scrambled symbols on a first input of a descrambling device implementing a reversible n-valued descrambling function, the descrambling device having the first and a second input and an output, wherein: the reversible n-valued descrambling function reverses a corresponding n-valued scrambling function; the second input of the descrambling device is connected to the output of one of the one or more devices; and the output is enabled to provide a plurality of signals representing p valued descrambled symbols; and associating the descrambler with a corresponding scrambler.
8. The method as claimed in claim 7 , wherein no inverters are used at inputs of n-valued reversible logic functions.
9. An n-valued scrambler for scrambling a first sequence of p n-valued symbols into a second sequence of p n-valued symbols with n>2 and p>2 and n and p being integers, wherein an n-valued symbol is represented by a signal, comprising:
an n-valued Linear Feedback Shift Register (LFSR) including:
an n-valued shift register with an input, the n-valued shift register containing q shift register elements with q being an integer and q<p, each shift register element enabled to hold an n-valued symbol; and
at least one device implementing an n-valued reversible logic function not being a modulo-n adder, the device including a first and a second input and an output;
a scrambling device implementing an n-valued reversible logic function, the scrambling device including:
a first input enabled to receive the first sequence of p n-valued symbols;
a second input, the second input of the scrambling device being connected to the output of the at least one device implementing an n-valued reversible logic function; and
an output, the output providing the second sequence of p n-valued symbols, and the output being connected to the input of the n-valued shift register; and
the n-valued scrambler corresponding to a descrambler which can recover the first sequence from the second sequence.
10. The n-valued scrambler as claimed in claim 9 , wherein at least one n-valued logic function is implemented in binary logic.
11. An n-valued descrambler for descrambling a first sequence of p n-valued symbols into a second sequence of p n-valued symbols with n>2 and p>1 and n and p being integers, wherein an n-valued symbol is represented by a signal, comprising:
an n-valued Linear Feedback Shift Register (LFSR) including:
an n-valued shift register with an input, the input enabled to receive the first sequence of p n-valued symbols; and
at least one device implementing an n-valued reversible logic function, the device including a first and a second input and an output;
a descrambling device implementing an n-valued reversible logic function, the descrambling function reversing a corresponding scrambling function not being a modulo-n adder, the descrambling device including:
a first input enabled to receive the first sequence of p n-valued symbols;
a second input, the second input of the descrambling device being connected to the output of the at least one device implementing an n-valued reversible logic function; and
an output, the output providing the second sequence of p n-valued symbols; and
the n-valued descrambler corresponding to a scrambler which scrambles the first sequence to the second sequence.
12. The n-valued descrambler as claimed in claim 11 , wherein at least one n-valued logic function is implemented in binary logic.
13. An n-valued scrambler for scrambling a first sequence of p n-valued symbols into a second sequence of p n-valued symbols with n>2 and p>2 and n and p being integers, wherein an n-valued symbol is represented by a signal, comprising:
an n-valued Linear Feedback Shift Register (LFSR) including:
an input and an output;
an n-valued shift register containing q shift register elements with q being an integer and q<p, each shift register element enabled to hold an n-valued symbol; and
at least one device implementing an n-valued logic function, the device including a first and a second input and an output;
a scrambling device comprising at least a first and a second input and an output implementing an n-valued reversible logic function not being a modulo-n adder, wherein:
the first input is enabled to receive the first sequence of p n-valued symbols;
the second input is connected to the output of the n-valued LFSR; and
the output of the scrambling device is connected to the input of the n-valued shift register;
a scrambler output providing the second sequence of p n-valued symbols; and
the n-valued scrambler corresponding to a descrambler that can recover the first sequence from the second sequence.
14. The n-valued scrambler as claimed in claim 13 , wherein the scrambling device implements a self-reversing n-valued logic function.
15. The n-valued scrambler as claimed in claim 13 , wherein at least one n-valued logic function is implemented in binary logic.
16. The n-valued scrambler as claimed in claim 13 , wherein the n-valued scrambler includes an implementation of a non-commutative n-valued logic function.
17. The n-valued scrambler as claimed in claim 13 , wherein the n-valued scrambler includes an implementation of an adder over a Galois Field GF(2 k ) of order 2 k with k>1 and k being an integer.
18. The n-valued scrambler as claimed in claim 13 , wherein the n-valued scrambler is implemented in a Digital Signal Processor.
19. An n-valued descrambler for descrambling a first sequence of p n-valued symbols into a second sequence of p n-valued symbols with n>2 and p>2 and n and p being integers, wherein an n-valued symbol is represented by a signal, comprising:
an n-valued Linear Feedback Shift Register (LFSR) including:
an output;
an n-valued shift register with an input, the input enabled to receive the first sequence of p n-valued symbols; and
at least one device implementing an n-valued logic function, the at least one device including a first and a second input and an output;
a descrambling device implementing an n-valued reversible logic function, the descrambling function reversing a corresponding scrambling function not being a modulo-n adder, the descrambling device including:
a first input enabled to receive the first sequence of p n-valued symbols;
a second input which is connected to the output of the LFSR; and
an output providing the second sequence of p n-valued symbols.
20. The n-valued descrambler as claimed in claim 19 , wherein the descrambling device implements a self-reversing n-valued logic function.
21. The n-valued descrambler as claimed in claim 19 , wherein at least one n-valued logic function is implemented in binary logic.
22. The n-valued descrambler as claimed in claim 19 , wherein the n-valued descrambler includes an implementation of a non-commutative n-valued logic function.
23. The n-valued descrambler as claimed in claim 19 , wherein the n-valued descrambler includes an implementation of an adder over a Galois Field GF(2 k ) of order 2 k with k>1 and k being an integer.
24. The n-valued descrambler as claimed in claim 19 , wherein the descrambler is self-synchronizing.
25. The n-valued scrambler as claimed in claim 19 , wherein the n-valued descrambler is implemented in a Digital Signal Processor.
26. An n-valued scrambler for scrambling p n-state symbols with p>1 and n>2 with n and D being integers into p scrambled n-valued symbols, wherein an n-valued symbol is represented by a signal, comprising: an input, the input enabled to receive the signals representing the p n-valued symbols; an n-valued Linear Feedback Shift Register (LFSR) comprising q shift register elements with q<p and q being an integer greater than 1; an implementation of a non-commutative n-valued logic function, having at least a first input and a second input and an output; and an output of the scrambler enabled to provide the signals representing the p scrambled n-valued symbols.