Multi-valued digital information retaining elements and memory devices
Discussed are models and methods to create stable binary and non-binary sequential devices including one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input information retaining devices from two logic functions are discussed. Memory elements using the information retaining devices and methods are also discussed. Methods and apparatus for n-valued memory devices including n-valued inverters with feedback are discussed. Binary and non-binary information retaining elements with two logic functions and two independent inputs are discussed. Also discussed are n-valued gating devices that can be combined with n-valued information retaining devices to form n-valued memory devices. Methods and apparatus for single non-binary n-valued logic function latches are discussed. Single non-binary n-valued function methods realizing (n−1)-valued latching methods controlled by an nth state are also discussed. Two non-binary n-valued logic functions based memory devices retaining the value of a first input and controlled by a second input are discussed. Ternary, 4-valued and n-valued true latches are discussed.
1. An n-valued apparatus for retaining information, comprising:
an implementation of a logical structure, the logical structure being completely determined by at least a first n-valued logic function, but by not more than 2 n-valued logic functions with feedback with n>3 in compliance with a causal switching model for producing an output signal that is stable, the first n-valued logic function including:
a first and a second input, the first input enabled to receive a first signal being in one of n states, and the second input enabled to receive a second signal being in one of p states, with p≧n−1;
an output enabled to provide an output signal, the output signal being in one of p states, each state being uniquely and reversibly related to one of p states of the first signal provided on the first input; and
the second signal being dependent from the output signal.
2. The n-valued apparatus as claimed in claim 1 , wherein p=n and the logical structure further comprising:
a second n-valued logic function, the second n-valued logic function having a first input, a second input and an output; wherein
the output of the first n-valued logic function is connected to the second input of the second n-valued logic function, and
the output of the second n-valued logic function is connected to the second input of the first n-valued logic function;
the first input of the first n-valued logic function being a first input of the n-valued apparatus;
the first input of the second n-valued logic function being a second input of the n-valued apparatus; and
the output of the first n-valued logic function being an output of the n-valued apparatus.
3. The n-valued apparatus as claimed in claim 2 , wherein:
the second input of the n-valued apparatus is capable to receive a second n-valued signal, the second n-valued signal having a first state; and
the output of the n-valued apparatus continuing to provide the n-valued output signal that is uniquely and reversibly related to the signal on the first input of the first device when the second n-valued signal is changed from the first state to a second state.
4. The n-valued apparatus as claimed in claim 3 , wherein:
the second n-valued signal is in the second state;
the first n-valued signal is put in a third of n states; and
the output of the n-valued apparatus continues to provide the n-valued output signal of claim 3 when the second n-valued signal was in the first state.
5. The n-valued apparatus as claimed in claim 4 , wherein the first n-valued logic function and the second n-valued logic function are identical n-valued logic functions.
6. The n-valued apparatus as claimed in claim 1 , wherein
p=n−1; and
the output of the first n-valued logic function is connected to the second input of the first n-valued logic function.
7. The n-valued apparatus as claimed in claim 6 , wherein the output signal does not change in state when the signal on the first input is changed from one in (n−1) states to an n th state.
8. The n-valued device as claimed in claim 7 , further comprising a gating device including:
a first input enabled to receive a signal being in one of (n- 1 ) states, a control input enabled to receive a signal having one of at least two states, and an output enabled to provide an output signal being in one of n states, the output of the gating device being connected to the first input of the first device and wherein:
the output of the gating device provides the signal received on the first input of the gating device when the control input receives a signal in a first state and the output of the gating device provides a signal in an nth state when the control input receives a signal not in a first state.
9. The n-valued apparatus as claimed in claim 2 , wherein the first input of the second n-valued logic function is connected to the first input of the first n-valued logic function, and further comprising:
a gating device having:
a first and a second input, each capable to receive an n-valued signal;
a control input, capable to receive a signal having at least a first and a second state;
an output, enabled to provide an n-valued signal; and wherein
the output of the n-valued apparatus is connected to the second input of the gating device;
the output of the gating device is connected to the first input of the n-valued apparatus;
the first input of the gating device is conducting to the output of the gating device when the control input receives a signal in a first state; and
the second input of the gating device is conducting to the output of the gating device when the control input receives a signal not in a first state.
10. The n-valued apparatus as claimed in claim 2 , wherein:
the first input of the second n-valued function is connected to the first input of the first n-valued function.
11. The n-valued apparatus as claimed in claim 10 , wherein the first input of the second n-valued function is connected to the first input of the first n-valued function through a reversible n-valued inverter.
12. The n-valued apparatus as claimed in claim 1 , wherein the output of the
first n-valued logic function is connected with the second input of the first n-valued logic function and p=n.
13. The n-valued apparatus as claimed in claim 12 , wherein the output of the first n-valued logic function is connected to the second input through a reversible n-valued inverter.
14. The n-valued device as claimed in claim 12 , further comprising a gating device including:
a first input enabled to receive a signal being in one of n states, a second input being connected to the output of the first device, a control input, and an output enabled to provide an output signal being in one of n states, the output being connected to the first input of the first device, and wherein:
the output of the gating device provides the signal received on the first input of the gating device when the control input receives a signal in a first state and the output of the gating device provides the signal provided on the second input of the gating device when the control input receives a signal in a second state.
15. The n-valued device as claimed in claim 1 , wherein a state of a truth table that determines the n-valued logic function is represented by an electrical signal.
16. The n-valued device as claimed in claim 1 , wherein a state of a truth table that determines the n-valued logic function is represented by an optical signal.