Symbol reconstruction in Reed-Solomon codes
Symbol reconstruction methods by applying Galois Field arithmetic to Reed Solomon codewords have been disclosed. Reconstruction methods by applying n-valued reversing logic functions are also provided. A correct codeword can be selected from calculated codewords by comparing a calculated codeword with the Reed-Solomon codeword in error. A correct codeword can also be found by comparing a codeword in error with possible (p,k) codewords. Non Galois Field Reed Solomon coders are disclosed. Methods for correcting symbols in errors that have been identified as being in error are provided. Apparatus that implement the error correction methods are disclosed. Systems, including communication and storage systems that use the disclosed methods are also provided.
1. A method for decoding a (p,k) Reed-Solomon (RS) codeword having p n-valued symbols with n>2 and n being an integer, k of the p n-valued symbols being information symbols with p>1 and k>1, comprising evaluating a predetermined expression implemented on a processor, which contains at least one n-valued logic function defined by a truth table that determines an n-valued output symbol based on at least a first and a second n-valued input symbol and includes one or more n-valued symbols of the (p,k) Reed-Solomon (RS) codeword that are not in error as variables of which at least one is multiplied with an n-valued factor not being 0 or 1 and which generates a corrected n-valued symbol in the codeword, wherein each symbol is represented by a signal and wherein the predetermined expression is defined by at least one of a plurality of n-valued check symbol expressions with fixed n-valued coefficients and each n-valued check symbol expression in the plurality of n-valued check symbol expressions determines a value of an n-valued check symbol in the Reed-Solomon (RS) codeword.
2. The method as claimed in claim 1 , further comprising:
determining a number of common n-valued symbols that a calculated codeword has in common with n-valued symbols in corresponding positions in the (p,k) RS codeword; and
determining the calculated codeword as a correct codeword if the number of common n-valued symbols is at least k+(p−k)/2.
3. The method as claimed in claim 1 , further comprising selecting the predetermined expression from a plurality of predetermined expressions based on an n-valued symbol in the (p,k) RS codeword known to be in error.
4. The method as claimed in claim 1 , further comprising correcting up to (p−k)/2 errors.
5. The method of claim 1 , wherein n is a multiple of 2.
6. The method of claim 1 , wherein an n-valued symbol is represented by one or more binary symbols.
7. The method of claim 1 , further comprising:
creating a plurality of calculated codewords; and
selecting from the plurality of calculated codewords as a correct codeword a calculated codeword that has at least k+(p−k)/2 symbols in corresponding positions in common with the (p,k) RS codeword.
8. The method of claim 1 , further comprising:
inputting k n-valued symbols on an n-valued Linear Feedback Shift Register (LFSR) having at least one n-valued logic function which is not an adder over GF(n);
outputting (p−k) n-valued symbols on an output of the LFSR; and
combining the k n-valued symbols with the (p−k) outputted n-valued symbols to form the (p,k) Reed-Solomon (RS) codeword with p n-valued symbols.
9. The method as claimed in claim 8 , wherein the n-valued logic function in the LFSR is implemented by an adder over GF(n) with two inputs with an n-valued inverter at an input, the n-valued inverter not being a multiplier over GF(n).
10. The method as claimed in claim 8 , wherein the applied LFSR is in Galois configuration.
11. An apparatus for decoding a (p,k) Reed Solomon (RS) codeword of p n-valued symbols with n>2 and n being an integer of which k n-valued symbols are information symbols with p>1 and k>1 with at least one n-valued symbol in error, including:
a processor enabled to execute instructions to perform a step:
the processor evaluating a predetermined expression which includes one or more n-valued symbols of the (p,k) RS codeword not in error as variables of which at least one is multiplied with an n-valued factor not being 0 or 1 and which generates a correct value of the at least one n-valued symbol in error in a calculated codeword, wherein each symbol is represented by a signal and wherein the predetermined expression is defined by at least one of a plurality of n-valued check symbol expressions with fixed n-valued coefficients and each n-valued check symbol expression in the plurality of n-valued check symbol expressions determines a value of an n-valued check symbol in the Reed-Solomon (RS) codeword.
12. The apparatus as claimed in claim 11 , the processor further enabled to perform the steps:
determining a number of n-valued symbols that the calculated codeword has in common with n-valued symbols in corresponding positions in the (p,k) RS codeword; and
determining the calculated codeword as a correct codeword if the number of n-valued symbols is at least k+(p−k)/2.
13. The apparatus as claimed in claim 11 , the processor further enabled to perform a step of selecting the predetermined expression from a plurality of predetermined expressions based on an n-valued symbol in the (p,k) RS codeword known to be in error.
14. The apparatus of claim 11 , wherein n is a multiple of 2.
15. The apparatus of claim 11 , wherein an n-valued symbol is represented by one or more binary symbols.
16. The apparatus of claim 11 , the processor further enabled to perform the steps of:
creating a plurality of calculated codewords; and
selecting from the plurality of calculated codewords as a correct codeword a calculated codeword that has at least k+(p−k)/2 symbols in corresponding positions in common with the (p,k) RS codeword.
17. A system for decoding a (p,k) Reed-Solomon (RS) codeword having p n-valued symbols with n>2 and n being an integer of which k n-valued symbols are information symbols, comprising:
a processor enabled to execute instructions to perform a step:
evaluating a predetermined expression which includes only one or more n-valued symbols of the (p,k) Reed-Solomon (RS) codeword that are not in error as external variables of which at least one is multiplied with an n-valued factor not being 0 or 1 and which generates a corrected n-valued symbol in the codeword, wherein each symbol is represented by a signal and wherein the predetermined expression is defined by at least one of a plurality of n-valued check symbol expressions with fixed n-valued coefficients and each n-valued check symbol expression in the plurality of n-valued check symbol expressions determines a value of an n-valued check symbol in the Reed-Solomon (RS) codeword.
18. The system as claimed in claim 17 , further comprising the processor enabled to execute instructions to perform a step selecting the n-valued logic expression from a plurality of expressions based on an n-valued symbol in the (p,k) RS codeword known to be in error.
19. The system as claimed in claim 17 , further comprising the processor enabled to execute instructions to perform the steps:
determining a number of common n-valued symbols that the calculated codeword has in common with n-valued symbols in corresponding positions in the (p,k) RS codeword; and
determining the calculated codeword as the correct codeword if the number of common n-valued symbols is at least k+(p−k)/2.
20. The system as claimed in claim 17 , wherein the system is a communication system.
21. The system as claimed in claim 17 , wherein the system is a data storage system.