GENERATION AND SELF-SYNCHRONIZING DETECTION OF SEQUENCES USING ADDRESSABLE MEMORIES

1 . An apparatus for implementing an n-valued LFSR with n≧2 of k elements with k≧2 comprising:

an addressable memory with n k memory lines, wherein:

each memory line has an address;

each memory line can be individually enabled;

each memory line is able to store k symbols; and

each memory line when enabled outputs k symbols on k individual memory line outputs;

an address decoder with k inputs;

d devices, each implementing a reversible n-valued logic function, connected to (d+1) memory line outputs with d+1≦k and connected to realize an n-valued LFSR logic unit with an output adapted to be an apparatus output;

(k−1) of the k memory line outputs being connected to (k−1) inputs of the address decoder; and

a k th input of the address decoder not being connected to a memory line output and being an apparatus input.

2 . The apparatus as claimed in claim 1 , further comprising a connection between the apparatus output and the apparatus input and wherein the output of the apparatus is adapted for outputting a sequence of n-valued symbols.

3 . The apparatus as claimed in claim 2 , wherein the memory line representing a forbidden word is omitted.

4 . The apparatus as claimed in claim 1 , for scrambling a first sequence of n-valued symbols into a second sequence of n-valued symbols, further comprising:

a device with a first and a second input and an output implementing a first reversible n-valued logic function wherein:

the first input of the device is connected to the apparatus output;

the second input receives the first sequence of n-valued symbols; and

the output of the device outputs the second sequence of n-valued symbols; and

a connection between the output of the device and the apparatus input.

5 . The apparatus as claimed in claim 1 , for descrambling a first sequence of n-valued symbols into a second sequence of n-valued symbols, further comprising:

a device with a first and a second input and an output implementing a first reversible n-valued logic function wherein:

the first input of the device is connected to the apparatus output;

the second input of the device receives a first sequence of n-valued symbols;

the output of the device provides the second sequence of n-valued symbols; and

a connection between the second input of the device and the apparatus input to provide the first sequence on the apparatus input.

6 . The apparatus as claimed in claim 5 , wherein the first sequence is created by a scrambler having a device implementing a second reversible n-valued logic function and the first reversible n-valued logic function reverses the second reversible n-valued logic function.

7 . An apparatus for self synchronized detection of a Gold sequence formed by two different n-valued LFSRs of k elements, comprising:

an addressable memory with a plurality of memory lines that can be individually enabled and that each can store (2k−1+q) n-valued symbols and having (2k−1+q) individual memory outputs for an enabled memory line, wherein:

(2k−1) of the (2k−1+q) symbols are part of a unique word of 2k n-valued symbols that occurs in one of a set of Gold sequences;

q symbols of the (2k−1+q) symbols are an indicator of the specific Gold sequence that a word corresponding to an address belongs to;

an address decoder with 2k individual inputs;

(2k−1) individual memory outputs being connected to (2k−1) individual inputs of the address decoder; and

one first individual input of the address decoder not being connected to one of 2k−1 individual memory outputs being adapted to accept a sequence of n-valued symbols.

8 . The apparatus as claimed in claim 7 , further comprising a module for processing the q indicator symbols.

9 . A method for implementing an n-valued LFSR of k elements comprising:

applying an addressable memory with n k memory lines wherein each memory line can store k symbols and each of the n k memory lines can be individually enabled;

outputting the k symbols of an enabled memory line on k individual memory outputs;

inputting (k−1) of k individual memory outputs to (k−1) individual inputs of an address decoder of the addressable memory having k individual inputs;

processing the symbols provided on the k individual memory outputs according to an n-valued LFSR logic unit and providing the result on a first output; and

adapting a k th input of k individual inputs of the address decoder as a first input to receive an n-valued symbol.

10 . The method as claimed in claim 9 , for generating a sequence of n-valued symbols further comprising:

a) initiating a first address on the address decoder;

b) providing an n-valued symbol available on the first output to the first input;

c) outputting the symbol available on the first output on a system output;

d) initiating a next address; and

e) repeating steps b) to d) until all n-valued symbols of the sequence have been generated.

11 . The method as claimed in claim 10 , wherein the addressable memory has no memory line representing a forbidden state for generating a sequence.

12 . The method as claimed in claim 9 , for scrambling a first sequence of n-valued symbols into a second sequence of n-valued symbols, further comprising:

a) initiating a first address on the address decoder;

b) providing an n-valued symbol available on the first output to a first input of a reversible n-valued logic function with a first and second input and an output;

c) providing an n-valued symbol of the first sequence of n-valued symbols on the second input of the reversible n-valued logic function;

d) generating an n-valued symbol of the second sequence of n-valued symbols on the output of the reversible n-valued logic function resulting from the symbols on the first and second input of the reversible n-valued logic function;

e) providing the n-valued symbol of the second sequence available on the output of the reversible n-valued logic function to the first input and to a system output;

f) initiating a next address; and

g) repeating steps b) to f) until all symbols of the first sequence have been scrambled.

13 . The method as claimed in claim 9 , for descrambling a first sequence of n-valued symbols into a second sequence of n-valued symbols, further comprising:

a) initiating a first address on the address decoder;

b) providing a symbol available on the first output to a first input of a first reversible n-valued logic function with a first and second input and an output;

c) providing an n-valued symbol of the first sequence of n-valued symbols on the second input of the first reversible n-valued logic function and on the first input;

d) generating an n-valued symbol of the second sequence on the output of the first reversible n-valued logic function resulting from the symbols on the first and second input of the first reversible n-valued logic function;

e) providing the n-valued symbol of the second sequence on the output of the first reversible n-valued logic function to a system output;

f) initiating a next address; and

g) repeating steps b) to f) until all n-valued symbols of the first sequence have been descrambled.

14 . The method as claimed in claim 13 , wherein the first sequence is created by a scrambling method applying a second reversible n-valued logic function and the first reversible n-valued logic function reverses the second reversible n-valued logic function.

15 . The method as claimed in claim 13 , wherein the first sequence is created by a scrambling method applying an addressable memory that is initiated on a second address and the first address is identical to the second address.

16 . A method for self synchronized detection of a Gold sequence formed by two n-valued LFSRs of k elements from a first sequence of n-valued symbols, comprising:

a) initializing an addressable memory with at plurality of memory lines which can be individually addressed by an address decoder with 2k individual inputs wherein:

each memory line can store (2k−1+q) n-valued symbols;

an enabled memory line has (2k−1+q) individual memory outputs;

(2k−1) of the (2k−1+q) symbols stored in each memory line are part of a unique word of 2k n-valued symbols that occurs in one of a set of Gold sequence; and

q symbols of the (2k−1+q) symbols are an indicator of a Gold sequence that a word corresponding to an address belongs to;

(2k−1) individual memory outputs being connected to (2k−1) individual inputs of the address decoder;

b) initiating a first address of the addressable memory;

c) providing an n-valued symbol of the first sequence on a first individual input of the address decoder not being connected to one of 2k−1 individual memory outputs;

d) outputting the q symbols of the enabled memory line representing the indicator to a processing module with an output;

e) initiating a next address; and

f) repeating steps c) to e) a pre-determined number of times.

17 . The method as claimed in claim 16 , wherein the output of the processing module provides a confirmation signal when a predefined criterion of indicators has been met.

18 . A method for detection of a Gold sequence formed by n-valued LFSRs of k elements from a first sequence of n-valued symbols comprising:

a) initializing an addressable memory with at plurality of memory lines which can be individually addressed by an address decoder with 2k individual inputs wherein:

each memory line stores q indicator symbols which are an indicator of a specific Gold sequence;

b) deserializing 2k symbols of the first sequence as an address for the address coder;

c) enabling a memory line corresponding with the address formed by the deserialized 2k symbols;

d) outputting q indicator symbols to a processing module with an output; and

e) repeating steps b) to d) a predefined number of times.

19 . The method as claimed in claim 18 , wherein the output of the processing module provides a confirmation signal when a predefined criterion of indicators has been met.