SCRAMBLING AND SELF-SYNCHRONIZING DESCRAMBLING METHODS FOR BINARY AND NON-BINARY DIGITAL SIGNALS NOT USING LFSRs
The invention discloses methods to create binary and n-valued sequences using addressable memory methods. Methods and apparatus to scramble and descramble binary and non-binary sequences using addressable memory methods are also disclosed. The invention further discloses methods using addressable memory to scramble binary and non-binary sequences and corresponding self-synchronizing descrambling methods with limited error propagation. Scrambling and descrambling methods for binary and non-binary methods are disclosed that can not or not easily be realized with LFSR based methods. Methods for dynamically changing functions in scramblers and descramblers are also disclosed.
1 . A method of generating a scrambled sequence from an input sequence using a plurality of addresses, each of the plurality of addresses being associated with a multi-symbol word, comprising:
selecting one of the plurality of addresses; and
processing a symbol from a first multi-symbol word associated with the selected address and a symbol from the input sequence with a function to generate a next symbol for the scrambled sequence.
2 . The method of claim 1 , wherein the function is an n-valued reversible logic function. and an address and a multi-symbol word both have m n-valued symbols with m≧2.
3 . The method of claim 1 , further comprising:
using the next symbol to generate another one of the plurality of addresses; and
processing a symbol from another multi-symbol word that is associated with the generated address and another symbol from the input sequence with the function to generate a new next symbol.
4 . The method of claim 3 , wherein the symbol of the first multi-symbol word and the symbol of the another multi-symbol word are a first symbol in the multi-symbol words.
5 . The method of claim 3 , comprising repeating the steps of claim 3 until the input sequence is completely scrambled.
6 . The method of claim 2 , wherein an address and an associated multi-symbol word have (m−1) consecutive symbols in common.
7 . The method as claimed in claim 2 , wherein no address is identical to an associated multi-symbol word.
8 . The method as claimed in claim 2 , wherein there are n m different addresses.
9 . A method of generating a descrambled sequence from an input sequence using a plurality of addresses, each of the plurality of addresses being associated with a multi-symbol word, comprising:
selecting one of the plurality of addresses; and
processing a symbol from a first multi-symbol word associated with the selected address and a symbol from the input sequence with a function to generate a next symbol for the descrambled sequence.
10 . The method of claim 9 , wherein the function is an n-valued reversible logic function. and an address and a multi-symbol word both have m n-valued symbols with m≧2.
11 . The method of claim 9 , further comprising:
using the symbol from the input sequence to generate another one of the plurality of addresses; and
processing a symbol from another multi-symbol word that is associated with the generated address and another symbol from the input sequence with the function to generate a new next symbol.
12 . The method of claim 11 , wherein the symbol of the first multi-symbol word and the symbol of the another multi-symbol word are a first symbol in the multi-symbol words.
13 . The method of claim 11 , comprising repeating the steps of claim 11 until the input sequence is completely scrambled.
14 . The method of claim 10 , wherein an address and an associated multi-symbol word have (m−1) consecutive symbols in common.
15 . The method as claimed in claim 10 , wherein no address is identical to an associated multi-symbol word.
16 . The method as claimed in claim 10 , wherein there are n m different addresses.
17 . An apparatus for scrambling a sequence of n-valued symbols, comprising:
an addressable memory having a plurality of memory lines and an address decoder, wherein:
each memory line has an address with an associated word of m n-valued symbols; and
a memory line can be enabled by the address decoder to make the m n-valued symbols of the associated word available on m memory outputs;
the address decoder having m inputs, forming an address of a memory line;
an n-valued device, having a first and a second input and an output, implementing a reversible n-valued logic function;
a first of the m memory outputs being connected with the first input of the n-valued device;
the second input of the n-valued device being configured to receive a symbol from the sequence;
the m−1 memory outputs, not including the first of the m memory outputs, being connected to m−1 inputs of the address decoder;
the output of the n-valued device being connected to the one of m address decoder inputs not directly connected to a memory output; and wherein
a scrambled symbol can be provided on the output of the n-valued device.
18 . The apparatus as claimed in claim 17 , wherein the plurality of words is n m .
19 . An apparatus for descrambling a sequence of n-valued symbols, comprising:
an addressable memory having a plurality of memory lines and an address decoder, wherein:
each memory line has an address with an associated word of m n-valued symbols; and
a memory line can be enabled by the address decoder to make the m n-valued symbols of the associated word available on m memory outputs;
the address decoder having m inputs, forming an address of a memory line;
an n-valued device, having a first and a second input and an output, implementing a reversible n-valued logic function;
a first of the m memory outputs being connected with the first input of the n-valued device;
the second input of the n-valued device being configured to receive a symbol from the sequence;
the m−1 memory outputs, not including the first of the m memory outputs, being connected to m−1 inputs of the address decoder;
the one of m address decoder inputs not directly connected to a memory output being configured to receive a symbol from the sequence; and
the output of the n-valued device being configured to provide a descrambled symbol.
20 . The apparatus as claimed in claim 19 , wherein the plurality of words is n m .