Binary digital latches not using only NAND or NOR circuits
A switching model to create stable binary sequential devices comprised of one or more logic functions with feedback of which an output signal is uniquely related to an input signal is applied to possible binary logic functions. Static latches of commutative and non-commutative binary functions are designed by using the switching model. Latches can be realized by individually controlled gates sometimes with inverters. Optical and electro-optical latches are disclosed. The application of transmission gates to realize latches is also disclosed.
1. A binary memory latch, comprising:
a circuit having a first and a second input and an output implementing a logical structure which is completely determined by a combination of a first and a second binary logic function, each binary logic function being determined by a truth table, wherein
each binary logic function in the combination having a first input and a second input and an output of which a state is completely determined by a state of the first input and a state of the second input;
the output of the first logic function is connected to the second input of the second logic function and the output of the second logic function is connected to the second input of the first logic function; and
at least one of the first and the second binary logic function is determined by a truth table selected from the group consisting of:
a first truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table:
X
Y
OUT
0
0
0
0
1
0
1
0
1
1
1
0;
a second truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table:
X
Y
OUT
0
0
1
0
1
0
1
0
1
1
1
1;
a third truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table:
X
Y
OUT
0
0
1
0
1
1
1
0
0
1
1
1;
and
a fourth truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents a state of the output of a binary logic function as provided by the following table:
X
Y
OUT
0
0
0
0
1
1
1
0
0
1
1
;0
and wherein
the first input of the circuit is the first input of the first logic function;
the second input of the circuit is the first input of the second logic function; and
the output of the circuit is enabled to provide a binary signal, the output of the circuit being equivalent to either the output of the first logic function or the output of the second function.
2. The latch as claimed in claim 1 , wherein the first and the second logic function both are determined by the first truth table.
3. The latch as claimed in claim 1 , wherein the first and the second logic function both are determined by the third truth table.
4. The latch as claimed in claim 1 , wherein the first logic function is determined by the first truth table and the second logic function is the binary NOR function.
5. The latch as claimed in claim 1 , wherein the first logic function is the binary NAND function; and the second logic function is determined by the second truth table.
6. The latch as claimed in claim 1 , wherein the first logic function is determined by the third truth table and the second logic function is determined by the fourth truth table.
7. The latch as claimed in claim 1 , wherein the first logic function is the binary AND function and the second logic function is determined by the third truth table.
8. The latch as claimed in claim 1 , wherein the first logic function is the binary NAND function and the second logic function is determined by the second truth table.
9. The latch as claimed in claim 1 , wherein the first logic function is determined by the fourth truth table and the second logic function is the binary OR function.
10. A binary memory latch comprising:
a first individually controlled gate with an input, an output and a control input wherein a signal representing a binary logic state provided on the input will be provided on the output when a control signal provided on the control input represents the logic state 0, and a signal representing the logic state 0 will be provided on the output when a control signal representing the logic state 1 is provided on the control input; a second individually controlled gate functionally identical to the first individually controlled gate with an input an output and a control input; the output of the first individually controlled gate being connected to the control input of the second individually controlled gate; and the output of the second individually controlled gate being connected to the control input of the first individually controlled gate.
11. The latch as claimed in claim 10 , wherein all the signals are optical signals.
12. The latch as claimed in claim 10 , wherein all the signals are electrical signals.
13. The latch as claimed in claim 10 , wherein the signals provided on the inputs, the control inputs and the outputs are optical signals.
14. A binary memory latch, comprising:
a first transmission gate with an input, an output, a first type control input and a second type control input;
the first transmission gate being turned off when the first type control input is at a first binary state and the second type control input is at a second binary state;
the first transmission gate being turned on when the first type control input is at a second binary state and the second type control input is at a first binary state;
a second transmission gate having an input, an output, a first type control input and a second type control input and being functionally identical to the first transmission gate; the first type control input of the first transmission gate being connected to the output of the first transmission gate and the second type control input of the first transmission gate being connected to the output of the second transmission gate; and
the first type control input of the second transmission gate being connected to the output of the second transmission gate and the second type control input of the second transmission gate being connected to the output of the first transmission gate.
15. The binary memory latch as claimed in claim 14 wherein the first type control input is an n-type control input and the second type control input is a p-type control input.
16. The binary memory latch as claimed in claim 15 wherein the first binary state is 0 and the second binary state is 1.
17. The binary memory latch as claimed in claim 14 wherein a turned off gate is non-conducting and a turned on gate is conducting.
18. The latch as claimed in claim 1 , wherein the circuit is implemented by using an individually controlled switch having an input, a control input and an output, each able to be in one of two states, and wherein:
the output assumes a state of the input whenever the control input is in a first of two states; and
the output assumes a state corresponding with an absence of signal whenever the control input is not in a first of two states.
19. A binary memory latch, comprising:
a circuit having a first and a second input and an output implementing a logical structure which is completely determined by a combination of a first and a second binary logic function, wherein:
each binary logic function in the combination having a first input and a second input and an output of which a state is determined only by a state of the first input and a state of the second input;
the output of the first logic function is connected to the second input of the second logic function and the output of the second logic function is connected to the second input of the first logic function; and
the first logic function is the binary OR functions and second logic function is the binary AND function; and wherein
the first input of the circuit is enabled to receive a binary signal, the first input of the circuit being equivalent to the first input of the first logic function;
the second input of the circuit is enabled to receive a binary signal, the second input of the circuit being equivalent to the first input of the second logic function; and
the output of the circuit enabled to provide a binary signal the output being equivalent to either the output of the first logic function or the output of the second function.
20. A binary memory latch, comprising:
a circuit having a first and a second input and an output implementing a logical structure which is completely determined by a combination of a first and a second binary logic function, wherein:
each binary logic function in the combination having a first input and a second input and an output of which a state is determined only by a state of the first input and a state of the second input;
the output of the first logic function is connected to the second input of the second logic function and the output of the second logic function is connected to the second input of the first logic function; and
the first logic function and the second logic function are both determined by a truth table wherein X represents a state of the first input, Y represents a state of the second input and OUT represents the state of the output of a binary logic function as provided by the following table:
X
Y
OUT
0
0
0
0
1
0
1
0
1
1
1
0;
and
the first input of the circuit is enabled to receive a binary signal, the first input of the circuit being equivalent to the first input of the first logic function;
the second input of the circuit is enabled to receive a binary signal, the second input of the circuit being equivalent to the first input of the second logic function; and
the output of the circuit enabled to provide a binary signal the output being equivalent to either the output of the first logic function or the output of the second function.