Method of manufacturing semiconductor device and semiconductor device
View Patent ↗Impurity ions are implanted into the silicon layer of an SOI substrate to achieve an ion concentration distribution which inhibits for a reduction in threshold voltage (Vth-rolloff) as a gate length is reduced. A reduction in potential barrier which runs from a drain region side is effectively inhibited to counter short channel effects resulting from a reduction in gate length attendant with miniaturization of SOI-MOSFETs.
1. A semiconductor device, comprising:
a silicon-on-insulator (SOI) substrate which includes a silicon substrate having an upper surface, a first insulating layer having a lower surface extending horizontally over the upper surface of the silicon substrate, and a silicon layer having a lower surface extending horizontally over an upper surface of the first insulating layer and a peak ion concentration along a vertical depth of the silicon layer which is located between an intermediate horizontal plane of the silicon layer and the lower surface of the silicon layer inclusive, wherein the intermediate horizontal plane extends horizontally within the silicon layer at half a vertical depth of the silicon layer;
a second insulating layer formed over an upper surface of the silicon layer of the SOI substrate; and
a gate electrode formed over the second insulating layer.
2. The semiconductor device according to claim 1 , wherein an ion concentration of the silicon layer is substantially homogeneous along the vertical depth of the silicon layer.
3. A semiconductor device, comprising:
a silicon-on-insulator (SOI) substrate which includes a silicon substrate having an upper surface, a first insulating layer having a lower surface extending horizontally over the upper surface of the silicon substrate, and a silicon layer having a lower surface extending horizontally over an upper surface of the first insulating layer and a peak ion concentration along a vertical depth of the silicon layer which is located at the vertical depth ½ Tsoi±0.1 Tsoi of the silicon layer, where Tsoi is an entire vertical depth of the silicon layer;
a second insulating layer formed over an upper surface of the silicon layer of the SOI substrate; and
a gate electrode formed over the second insulating layer.