IP Library Granted Patent US 7,095,667
Granted Patent B2
US 7,095,667 · App. 10/915,088 · Granted Aug 22, 2006

Noise resistant small signal sensing circuit for a memory device

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Quick Facts
Patent No.
US 7,095,667
App. No.
10/915,088
Granted
Aug 22, 2006
Kind
B2
Abstract

Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

Claims (11)

1. A method of sensing a data state of a memory cell, comprising:

periodically switching coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, the second configuration changing polarity of the integrator circuit from the first configuration;

periodically comparing output signals provided by the integrator circuit;

based on the comparison, generating an output signal having a voltage representative of a value; and

averaging the value of the output signal over a time period.

2. The method of claim 1 , further comprising amplifying the output signals provided by the integrator signal prior to the periodic comparison.

3. The method of claim 1 , further comprising:

providing a first current having a first polarity to a first of the output terminals of the integrator circuit and providing a second current having a second polarity opposite the first polarity to a second of the output terminals of the integrator circuit; and

switching the provision of the first and second currents to the first and second output terminals of the integrator circuit based on the value of the output signal.

4. The method of claim 1 wherein the switching occurs at a period greater than that at which the comparing occurs.

5. The method of claim 4 wherein the period of the switching is a multiple of that at which the comparing occurs.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →