Semiconductor devices and methods of fabricating the same
View Patent ↗As disclosed herein, a semiconductor device includes a gate and a silicon substrate having a field region and an active region. A gate dielectric layer formed on the upper surface of the active region of the silicon substrate and on a gate dielectric layer. The gate may include first and second sidewall dielectric layers sequentially formed on sidewalls of the gate, epitaxial silicon layers formed at both sides of the gate on the silicon substrate, first LDD regions formed in the silicon substrate below the second sidewall dielectric layers, second LDD regions formed at one sides of the first LDD regions below the epitaxial silicon layers, source/drain regions formed under the second LDD regions, and silicide layers formed on the gate and the source/drain regions.
1. A semiconductor gate device, comprising:
a silicon substrate having a field region and an active region;
a gate dielectric layer on an upper surface of the active region of the silicon substrate;
a gate on the gate dielectric layer;
first and second sidewall dielectric layers on sidewalls of the gate;
epitaxial silicon layers at both sides of the gate in trenches in the silicon substrate;
first LDD regions in the silicon substrata below the second sidewall dielectric layers;
second LDD regions at one side of the first LDD regions in the epitaxial silicon layers;
source/drain regions under the second LDD regions;
silicide layers on the gate and the second LDD regions; and
a field oxide layer in the field region, wherein a bottom surface of the silicide layers and an upper surface of the field oxide layer are higher than the upper surface of the silicon substrate under the gate dielectric layer, and an upper surface of the epitaxial silicon layers is higher than the upper surface of the field oxide layer.
2. The semiconductor gate device of claim 1 , wherein each of the silicide layers comprises a material selected from the group consisting of titanium silicide, cobalt silicide, nickel silicide, and platinum silicide.
3. A method for fabricating a semiconductor gate device, comprising:
defining a field region and an active region on a silicon substrate by forming a field oxide layer in the field region;
depositing a gate dielectric layer and a gate layer sequentially;
forming a gate by patterning the gate layer;
forming first sidewall dielectric layers by oxidizing sidewalls of the gate;
forming first LDD regions on the silicon substrate using the first sidewall dielectric layers and the gate;
forming second sidewall dielectric layers as spacers on one side of the first dielectric layers;
partially etching the first LDD regions using the second sidewall dielectric layers as a mask, to expose the silicon substrate and form a trench therein;
forming epitaxial silicon layers on the exposed silicon substrate through a selective epitaxial growth process such that an upper surface of the epitaxial silicon layers is higher than an upper surface of the field oxide layer;
forming second LDD regions and source/drain regions by injecting ions into the epitaxial silicon layers; and
forming silicide layers on surfaces of the gate and the epitaxial silicon layers trough a silicide process, wherein a bottom surface of the silicide layers and an upper surface of the field oxide layer are higher than an upper surface of the silicon substrate under the gate dielectric layer, and an upper surface of the epitaxial silicon layers is higher than the upper surface of the field oxide layer.
4. The method of claim 3 , wherein the forming the silicide layers comprises:
sputtering a silicide reactive material on an upper surface at the gate and the epitaxial silicon layers; and
annealing the silicon substrate on which the silicide reactive material is sputtered.
5. The method of claim 4 , wherein the silicide reactive material is selected from the group consisting of nickel, cobalt, platinum and titanium.
6. The method of claim 3 , wherein the epitaxial silicon layer is formed at a thickness in the range of 100˜1000 Å.
7. The semiconductor gate device of claim 1 , wherein the gate comprises polysilicon.
8. A memory device, comprising the semiconductor gate device of claim 1 .
9. The method of claim 6 , wherein the thickness of the epitaxial silicon layer provides margin for consumption during the silicide layer forming step.
10. The method of claim 6 , wherein the forming the second LDD regions and the source/drain regions comprises implanting ions at a dose and/or an implanting energy based on the thickness of the epitaxial silicon layer.
11. The method of claim 3 , wherein the forming to field oxide layer comprises local oxidation of silicon (LOCOS).
12. The method or claim 3 , wherein the forming the field oxide layer comprises a shallow trench isolation (STI) process.
13. The method of claim 3 , wherein the gate layer comprises polysilicon.
14. The method of claim 3 , wherein the forming the second sidewall dielectric layers comprises depositing a dielectric material on a surface of the silicon substrate, and etching the dielectric material.
15. The method of claim 14 , wherein the dielectric material comprises an oxide or a nitride.
16. The method of claim 3 , wherein the silicide process comprises annealing.