IP Library Granted Patent US 7,187,068
Granted Patent B2
US 7,187,068 · App. 10/917,142 · Granted Mar 6, 2007

Methods and apparatuses for providing stacked-die devices

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Quick Facts
Patent No.
US 7,187,068
App. No.
10/917,142
Granted
Mar 6, 2007
Kind
B2
Abstract

Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.

Claims (29)

1. An apparatus comprising:

a first substrate having a top surface and bottom surface;

a set of one or more dies attached to the top surface of the first substrate, the one or more dies extending above the top surface a first distance;

one or more interconnections formed on the top surface of the first substrate, the one or more interconnections extending above the top surface a second distance;

a planar encapsulant disposed upon the top surface of the first substrate and extending above the top surface a third distance, the third distance greater than the first distance and less than the second distance such that the one or more dies are encapsulated and a portion of the one or more interconnections are exposed; and

a second substrate above the first substrate, the second substrate having a bottom surface and one or more conductive pads formed on the bottom surface of the second substrate, each conductive pad extending from the bottom surface of the second substrate down to the second distance without extending to the third distance.

2. The apparatus of claim 1 wherein the one or more dies are attached to one another in a stacked-die configuration and the uppermost portion of an uppermost die extends above the top surface the first distance.

3. The apparatus of claim 1 wherein the one or more dies have associated wires, the associated wires extending above the top surface a fourth distance, the fourth distance less than the first distance such that the associated wires are encapsulated.

4. The apparatus of claim 1 wherein the encapsulant is a thermal setting material.

5. The apparatus of claim 1 wherein

the second substrate further has a top surface and a second set of one or more dies attached to the top surface of the second substrate, and each conductive pad is electrically coupled to a corresponding interconnection of the one or more interconnections formed on the top surface of the first substrate.

6. The apparatus of claim 4 wherein the thermal setting material is an epoxy.

7. The apparatus of claim 3 wherein the associated wires of one or more of the dies comprise wire-bonds.

8. The apparatus of claim 1 wherein one or more of the dies has a logic processor device implemented thereon.

9. A system comprising:

a first sub-package; and

a second sub-package, the second sub-package stacked atop the first sub-package and electrically connected thereto, each of the first sub-package and the second sub-package including a substrate having one or more dies attached to a top surface of the substrate and one or more interconnections formed upon the top surface of the substrate, and a stencil-printable encapsulant stencil-printed onto the top surface of the substrate such that the one or more dies are encapsulated and an upper portion of each of the one or more interconnections is exposed, wherein the encapsulant of the first sub-package has a planar top surface and the upper portion of each of the one or more interconnections of the first sub-package extends above the planar top surface, and the substrate of the second sub-package has one or more conductive pads formed on a bottom surface, each conductive pad extending down from the bottom surface of the substrate of the second sub-package, contacting a corresponding interconnection of the first sub-package, without extending to the planar top surface.

10. The system of claim 9 wherein each conductive pad is electrically coupled to the corresponding interconnection of the one or more interconnections formed upon the top surface of the substrate of the first sub-package.

11. The system of claim 10 further comprising:

one or more additional sub-packages stacked successively atop the second sub-package, each additional sub-package including a substrate having one or more dies attached to a top surface of the substrate and one or more interconnections formed upon the top surface of the substrate, and an encapsulant disposed upon the top surface of the substrate such that the one or more dies are encapsulated and an upper portion of each of the one or more interconnections is exposed, and one or more conductive areas formed on a bottom surface, each conductive area electrically coupled to a corresponding interconnection of the one or more interconnections formed upon the top surface of the substrate of an immediately preceding sub-package.

12. The system of claim 9 wherein the one or more dies are attached to one another in a stacked-die configuration.

13. The system of claim 9 wherein the one or more dies have associated wires, the associated wires completely encapsulated by the encapsulant.

14. The system of claim 13 wherein the associated wires of one or more of the dies comprise wire-bonds.

15. The system of claim 9 wherein the encapsulant is a thermal setting material.

16. The system of claim 15 wherein the thermal setting material is an epoxy.

17. The system of claim 9 wherein one or more of the dies implements a logic processor device.

18. The system of claim 16 wherein the thermal setting material contains a flux.

19. The system of claim 9 wherein the encapsulant contains 0–80% silica.

20. The system of claim 9 wherein the encapsulant contains a viscosity decreasing solvent.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030740/0823 →