Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
View Patent ↗A leadless type resin-sealed semiconductor package includes a resin enveloper having a mounting face to be applied to a wiring board, and at least one side face associated with the mounting face to produce an angled side edge. A semiconductor chip is encapsulated and sealed in the resin enveloper. An electrode terminal is partially buried in the angled side edge of the resin enveloper so as to be exposed to an outside, with the electrode terminal being electrically connected to the semiconductor chip. The electrode terminal is formed with a depression which is shaped so as to be opened to an outside when the resin enveloper is placed on the wiring board such that the mounting face of the resin enveloper is applied thereto.
1. A leadless type resin-sealed semiconductor package comprising:
a resin enveloper having a top face, a bottom face, and at least one side face extending between said top face and said bottom face, said bottom face serving as a mounting face to be applied to a wiring board;
a semiconductor chip encapsulated in said resin enveloper; and
at least one electrode terminal partially buried in said resin enveloper and having a first face which is exposed on the mounting face of said resin enveloper so as to be coplanar therewith, and a second face which is exposed on the side face of said resin enveloper so as to be coplanar therewith, said as least one electrode terminal being electrically connected to said semiconductor chip,
wherein said at least one electrode terminal is formed with a depression which is shaped so that faces defining said depression are exposed to an outside when said resin enveloper is placed on said wiring board such that the mounting face of said resin enveloper is applied thereto.
2. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein the faces defining the depression of said at least one electrode terminal are covered with a plating layer.
3. The leadless type resin-sealed semiconductor package as set forth in claim 2 , wherein said at least one electrode terminal is covered with a plating layer except for the second face of said at lest one electrode terminal.
4. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein the mounting face and the at least one side face said resin enveloper define a right angle.
5. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein said depression of said at least one electrode terminal is formed as a right-angled depression.
6. The leadless type resin-sealed semiconductor package as set forth in claim 1 , further comprising a plate-like mount encapsulated in said resin enveloper, said semiconductor chip being mounted on said plate-like mount.
7. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein said at least one electrode terminal has a plate-like mount portion extended therefrom, said semiconductor chip being mounted on said plate-like mount portion.
8. The leadless type resin-sealed semiconductor package as set forth in claim 7 , wherein said at least one electrode terminal is defined as a first electrode terminal which is electrically connected to at least one electrode pad formed on a top surface of said semiconductor chip, which package further comprises:
a second electrode terminal partially buried in said resin enveloper in substantially a same manner as said first electrode terminal, said plate-like mount portion being extended from said second electrode terminal; and
an electrode layer formed on a bottom surface of said semiconductor chip and electrically connected to said second electrode terminal.
9. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein said at least one electrode terminal is defined as a source electrode terminal, which package further comprises:
a gate electrode terminal partially buried in said resin enveloper in substantially a same manner as said source electrode terminal; and
a drain electrode terminal partially buried in said resin enveloper in substantially a same manner as said source electrode terminal,
wherein said respective source, gate and drain electrode terminals are electrically connected to source, gate and drain pads formed on said semiconductor chip.
10. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein said at least one electrode terminal is defined as a source electrode terminal, which package further comprises:
a gate electrode terminal partially buried in said resin enveloper in substantially a same manner as said source electrode terminal;
a drain electrode terminal partially buried in said resin enveloper in substantially a same manner as said source electrode terminal, said drain electrode terminal having a plate-like mount portion extended therefrom, said semiconductor chip being mounted on said plate-like mount portion; and
an electrode layer formed on a bottom surface of said semiconductor chip,
wherein said respective source and gate and drain electrode terminals are electrically connected to source and gate pads formed on said semiconductor chip, said drain electrode terminal being electrically connected to said electrode layer formed on the bottom surface of said semiconductor chip.
11. The leadless type resin-sealed semiconductor package as set forth in claim 1 , wherein the formation of said depression is carried out in such a manner that a peripheral area of both said first and second faces of said at least one electrode terminal is left.