Byte slice based DDR timing closure
View Patent ↗Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.
1. A method for synthesizing & laying out a dual data rate memory interface, said method comprising:
synthesizing a portion of the dual data rate memory;
replicating the portion; and
placing the synthesized portion and the replicated portions in proximity to a corresponding plurality of pads.
2. The method of claim 1 , wherein the portion comprises a plurality of input/outputs.
3. The method of claim 2 , wherein the plurality of input/outputs comprise a byte lane.
4. The method of claim 2 , wherein synthesizing the portion further comprises:
generating a macro, said macro synthesizing the portion.
5. The method of claim 4 , wherein said macro comprises a plurality of cells, each of said cells corresponding to a particular one of the plurality of input/outputs.
6. A computer readable media for synthesizing a dual data rate memory interface, said computer readable media comprising a plurality of instructions, the plurality of instructions comprising:
receiving a macro representing a portion of the dual data rate memory;
replicating the macro; and
placing the macro and the replicated macros in proximity to a corresponding plurality of pads.
7. The computer readable media of claim 6 , wherein the portion comprises a plurality of input/outputs.
8. The computer readable media of claim 7 , wherein the plurality of input/outputs comprise a byte lane.
9. The computer readable media of claim 6 , wherein said macro comprises a plurality of cells, each of said cells corresponding to a particular one of the plurality of input/outputs.