Dynamically reconfigurable precision signal delay test system for automatic test equipment
View Patent ↗A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.
1. An automated test equipment (ATE) system for generating precise signal transitions for application to the input pins of a circuit under test, comprising:
a single programmable time event generator having an input for a master clock and an output; and
a plurality of coarse output circuits coupled to receive pattern data from a pattern memory and wherein each coarse output circuit is coupled to the master clock input of said single programmable time event generator and to said output of said single programmable time event generator, said plurality of coarse output circuits for repositioning in time data state transition of said pattern data on a plurality of tester pins of said ATE system.
2. The system of claim 1 , wherein said single programmable time event generator comprises a memory for storing a plurality of values each specifying a relative time position of a time event with respect to said master clock.
3. The system of claim 1 , further comprising said pattern memory which is coupled to each of said plurality of coarse output circuits.
4. The system of claim 2 , wherein the pattern memory addresses the memory of the single programmable time event generator.
5. The system of claim 1 , wherein said single programmable time event generator causes a data transition on at least a portion of said plurality of coarse output circuits.
6. The system of claim 1 , wherein said single programmable time event generator comprises:
a memory for storing delay values specifying relative time positions of a time event relative to a master clock; and
a programmable delay element coupled to said memory and coupled to said plurality of coarse output circuits.
7. The system of claim 6 , wherein said single programmable time event generator further comprises:
an inverter coupled to said programmable delay element; and
an AND gate coupled to said programmable delay element.
8. The system of claim 1 , wherein each coarse output circuit comprises:
a coarse delay element coupled to said single programmable time event generator;
a register coupled to said coarse delay element; and
a latch coupled to said register and also coupled to said single programmable time event generator.
9. A circuit for generating signals for an Automatic Testing Equipment (ATE) system, said circuit comprising:
a pattern memory for containing pattern data for application to a set of tester pins;
a single programmable time event generator receiving a master clock and containing a set of programmable values for specifying relative time positions of timing signals with respect to said master clock; and
a plurality of coarse timing circuits coupled to said master clock, said single programmable time event generator and said pattern memory, wherein said coarse timing circuits are for applying said pattern data to said set of tester pins with said relative time positions of said master clock.
10. A circuit as described in claim 9 wherein said single programmable time event generator comprises a memory for storing said set of programmable values and wherein said pattern memory addresses said memory comprising said set of programmable values.
11. A circuit as described in claim 9 wherein said single programmable time event generator comprises:
a memory for storing said set of programmable values; and
a programmable delay element coupled to said master clock.
12. A circuit as described in claim 9 wherein each of said coarse timing circuits comprise:
a delay element coupled to receive said master clock;
a first sequential cell coupled to receive a respective bit of said pattern data and clocked by said delay element;
a second sequential cell clocked by said programmable delay element and receiving an output of said first sequential cell, said second sequential cell coupled to drive a respective tester pin of said set of tester pins.
13. A circuit as described in claim 12 wherein said pattern memory addresses said memory comprising said set of programmable values.
14. An automated test equipment (ATE) system for capturing at precise times the signal states from the output pins of a circuit under test, comprising:
a single programmable time event generator having an input for a master clock and an output and for storing values specifying relative time positions of timing signals relative to said master clock; and
a plurality of coarse capture circuits, wherein each coarse capture circuit is coupled to the master clock input of said single programmable time event generator, to said output of said single programmable time event generator and for receiving outputs from a device under test, said plurality of coarse capture circuits for capturing data from said device under test bsed on said relative time positions of said timing signals relative to said master clock.
15. The system of claim 14 , wherein said single programmable time event generator comprises a memory for storing said values specifying said relative time positions of said timing signals relative to said master clock.
16. The system of claim 15 , wherein said single programmable time event generator generates a precisely controlled timing signal using the values stored in said memory.
17. The system of claim 15 , further comprising a test pattern data memory coupled to address said memory of said single programmable time event generator and for storing a plurality of data defining states to be delivered to said device under test.
18. The system of claim 14 , wherein said single programmable time event generator comprises:
a memory for storing said values;
a programmable delay element coupled to said memory; and
an AND gate coupled to said programmable delay element.
19. The system of claim 14 , wherein each coarse capture circuit comprises:
a coarse delay element coupled to said single programmable time event generator;
a register coupled to said coarse delay element; and
a latch coupled to said register, wherein said latch is also coupled to said single programmable time event generator.
20. A circuit for capturing signals from a device under test in an Automatic Testing Equipment (ATE) system, said circuit comprising:
a pattern memory for containing pattern data for application to a first set of tester pins;
a single programmable time event generator receiving a master clock and containing a set of programmable values for specifying relative time positions of timing signals with respect to said master clock and coupled to said pattern memory; and
a plurality of coarse timing circuits coupled to said master clock, said single programmable time event generator, wherein said coarse timing circuits are for capturing output data from a second set of tester pins using said relative time positions of said master clock.
21. A circuit as described in claim 20 wherein said single programmable time event generator comprises a memory for storing said set of programmable values and wherein said pattern memory addresses said memory comprising said set of programmable values.
22. A circuit as described in claim 20 wherein said single programmable time event generator comprises:
a memory for storing said set of programmable values; and
a programmable delay element coupled to said master clock.
23. A circuit as described in claim 22 wherein each of said coarse timing circuits comprise:
a delay element coupled to receive said master clock;
a first sequential cell coupled to supply an output data value to a test data comparator circuit and clocked by said delay element; and
a second sequential cell clocked by said programmable delay element and supplying an input of said first sequential cell, said second sequential cell coupled to receive a respective tester pin output of said second set of tester pins.
24. A circuit as described in claim 23 wherein said pattern memory addresses said memory comprising said set of programmable values.
25. A circuit as described in claim 20 wherein each of said coarse timing circuits is coupled to a comparator.