IP Library › Assignment 027896/0018
Patent Assignment
Reel/Frame 027896/0018

Assignment of Assignor's Interest

Recorded: 2012-03-20 Received: 2012-03-20 Pages: 34
Assignor
VERIGY (SINGAPORE) PTE LTD
Executed: 2012-03-02
Assignee
ADVANTEST (SINGAPORE) PTE LTD
1, YISHUN AVENUE 7, SINGAPORE, SGX, 768923, SINGAPORE
Covered Properties (100)
Apparatus and Method for Wireless Testing of a Plurality of Transmit Paths and a Plurality of Receive Paths of an Electronic Device
Application: 13/392,500 →
Adjustable Gain Amplifier, Automated Test Equipment and Method for Adjusting a Gain of an Amplifier
Application: 13/392,492 →
Optimized Automated Test Equipment Multi-Path Receiver Concept
Application: 13/391,260 →
Emo Linkage Simplification
Application: 13/334,612 →
Re-Configurable Test Circuit, Method for Operating an Automated Test Equipment, Apparatus, Method and Computer Program for Setting Up an Automated Test Equipment
Application: 13/128,705 →
State Machine and Generator for Generating a Description of a State Machine Feedback Function
Application: 13/120,914 →
Method and Apparatus for Determining a Minimum/Maximum of a Plurality of Binary Values
Application: 12/532,834 →
Signal Distribution Structure and Method for Distributing a Signal
Application: 13/120,157 →
Data Processing Unit and a Method of Processing Data
Application: 13/119,958 →
Apparatus and Method for Estimating Data Relating to a Time Difference and Apparatus and Method for Calibrating a Delay Line
Application: 13/000,348 →
Method and Apparatus for the Determination of a Repetitive Bit Value Pattern
Application: 12/994,069 →
Apparatus and Systems for Processing Signals Between a Tester and a Plurality of Devices Under Test
Application: 12/974,950 →
Method of Sharing a Test Resource at a Plurality of Test Sites, Automated Test Equipment, Handler for Loading and Unloading Devices to Be Tested and Test System
Application: 12/865,327 →
Method and Apparatus for Determining Relevance Values for a Detection of a Fault on a Chip and for Determining a Fault Probability of a Location on a Chip
Application: 12/671,674 →
Computing Device for Enabling Concurrent Testing
Application: 12/889,117 →
Systems, Methods and Apparatus Using Virtual Appliances in a Semiconductor Test Environment
High Impedance, High Parallelism, High Temperature Memory Test System Architecture
Application: 12/849,700 →
System, Method and Computer Program for Detecting an Electrostatic Discharge Event
Application: 12/671,892 →
Chip Tester, Method for Providing Timing Information, Test Fixture Set, Apparatus for Post-Processing Propagation Delay Information, Method for Post-Processing Delay Information, Chip Test Set Up and Method for Testing Devices Under Test
Application: 12/674,644 →
Methods for Fabricating Circuit Boards
Application: 12/830,805 →
Test System and Method for Testing Electronic Devices Using a Pipelined Testing Architecture
Application: 12/821,027 →
Structures and Processes for Fabrication of Probe Card Assemblies with Multi-Layer Interconnect
Application: 12/525,051 →
Test Electronics to Device Under Test Interfaces, and Methods and Apparatus Using Same
Application: 12/626,506 →
Asynchronous Sigma-Delta Digital-Analog Converter
Application: 12/376,121 →
Methods, Apparatus and Articles of Manufacture for Testing a Plurality of Singulated Die
Application: 12/549,049 →
High Density Interconnect System for Ic Packages and Interconnect Assemblies
Application: 12/546,432 →
Method and Product for Testing a Device Under Test
Application: 12/490,281 →
Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies
Application: 12/517,528 →
Test Time Calculator
Application: 12/223,727 →
Decorrelation of Data by Using This Data
Application: 12/282,139 →
Time-To-Digital Conversion with Delay Contribution Determination of Delay Elements
Application: 12/279,723 →
Test Module with Blocks of Universal and Specific Resources
Application: 12/376,429 →
Calibrating Signals by Time Adjustment
Application: 12/281,477 →
Format Transformation of Test Data
Application: 12/293,075 →
Time-To-Digital Conversion with Calibration Pulse Injection
Application: 12/224,114 →
High Density Interconnect System Having Rapid Fabrication Cycle
Application: 12/354,520 →
Method and Apparatus for Producing Controlled Stresses and Stress Gradients in Sputtered Films
Application: 11/995,490 →
Transmit/Receive Unit, and Methods and Apparatus for Transmitting Signals Between Transmit/Receive Units
Application: 12/276,299 →
Methods and Apparatus That Selectively Use or Bypass a Remote Pin Electronics Block to Test at Least One Device Under Test
Application: 12/276,290 →
Massively Parallel Interface for Electronic Circuit
Application: 12/175,393 →
Multi-Stage Data Processor with Signal Repeater
Application: 12/084,834 →
Apparatus, Method, and Computer Program for Obtaining a Time-Domain-Reflection Response-Information
Application: 12/084,371 →
A Method of Fabricating a Probe Card Assembly Using Magnetically Aligned Electrical Contact Elements, a Stamped Construction Electrical Contact Element Usable with the Method, and a Standalone Probe Card Tester Formable Using the Method
Application: 12/109,522 →
Methods for Analyzing Scan Chains, and for Determining Numbers or Locations of Hold Time Faults in Scan Chains
Application: 12/058,768 →
Methods and Apparatus for Estimating a Position of a Stuck-at Defect in a Scan Chain of a Device Under Test
Application: 12/074,015 →
Parallel Test Circuit with Active Devices
Application: 12/035,378 →
Tester, Method for Testing a Device Under Test and Computer Program
Application: 11/989,731 →
Communication Circuit for a Bi-Directional Data Transmission
Application: 11/919,388 →
System and Method for Baseband Calibration
Application: 11/998,909 →
System and Method for Simulating a Semiconductor Wafer Prober and a Class Memory Test Handler
Application: 11/998,481 →
Screw-Less Latching System for Securing Load Boards
Application: 11/998,614 →
System and method for electronic testing of devices
Application: 11/998,616 →
System and Method for Electronic Testing of Devices
Application: 11/998,024 →
Dynamic Mask Memory for Serial Scan Testing
Application: 11/941,026 →
Locating Hold Time Violations in Scan Chains by Generating Patterns on Ate
Application: 11/931,847 →
High Density Interconnect System Having Rapid Fabrication Cycle
Application: 11/858,064 →
Method for Operating a Secure Semiconductor Ip Server to Support Failure Analysis
Application: 11/850,342 →
Wafer Boat for Semiconductor Testing
Application: 11/895,590 →
Error Catch Ram Support Using Fan-Out/Fan-in Matrix
Application: 11/895,512 →
Systems for Testing and Packaging Integrated Circuits
Application: 11/781,172 →
Resource Access Manager for Controlling Access to a Limited-Access Resource
Application: 11/810,510 →
Method and Apparatus for Displaying Test Data
Application: 11/740,670 →
Method and Apparatus for Singulated Die Testing
Application: 11/735,871 →
Clamp and Method for Operating Same
Application: 11/734,187 →
Operational Amplifier Selecting One of Inputs, and an Amplifying Apparatus Using the Op Amplifier the Verification Method
Application: 10/579,578 →
High Impedance, High Parallelism, High Temperature Memory Test System Architecture
Application: 11/689,585 →
System and Method for Electronic Testing of Multiple Memory Devices
Application: 11/726,542 →
System. Method and Apparatus Using at Least One Flex Circuit to Connect a Printed Circuit Board and a Socket Card Assembly That Are Oriented at a Right Angle to One Another
Application: 11/688,757 →
Feature-Oriented Test Program Development and Execution
Application: 11/724,448 →
High Voltage, High Frequency, High Reliability, High Density, High Temperature Automated Test Equipment (Ate) Switch Design
Application: 11/685,873 →
Solid High Aspect Ratio via Hole Used for Burn-in Boards, Wafer Sort Probe Cards, and Package Test Load Boards with Electronic Circuitry
Application: 11/685,866 →
Methods and Apparatus for Testing a Circuit
Application: 11/684,446 →
Process for Improving Design-Limited Yield by Localizing Potential Faults from Production Test Data
Application: 11/682,314 →
Apparatus for Locating a Defect in a Scan Chain While Testing Digital Logic
Application: 11/680,134 →
Evaluation of an Output Signal of a Device Under Test
Application: 11/647,118 →
Method and Apparatus for Improving Load Time for Automated Test Equipment
Application: 11/639,769 →
Automated Loader for Removing and Inserting Removable Devices to Improve Load Time for Automated Test Equipment
Application: 11/639,770 →
Forced Air Cooling of Components on a Probecard
Application: 11/639,010 →
Liquid Cooled Dut Card Interface for Wafer Sort Probing
Application: 11/638,819 →
Process for Identifying the Location of a Break in a Scan Chain in Real Time
Application: 11/609,899 →
Interconnect assemblies, and methods of forming interconnects
Application: 11/636,244 →
Interconnect Assemblies, and Methods of Forming Interconnects, Between Conductive Contact Bumps and Conductive Contact Pads
Application: 11/636,096 →
Process for Improving Design Limited Yield by Efficiently Capturing and Storing Production Test Data for Analysis Using Checksums, Hash Values, or Digital Fault Signatures
Application: 11/565,616 →
System and Method for Device Performance Characterization in Physical and Logical Domains with Ac Scan Testing
Application: 11/563,612 →
Method of Manufacturing a Pcb Having Improved Cooling
Application: 11/603,390 →
System and Method for Frequency Offset Testing
Application: 11/595,640 →
Massively Parallel Interface for Electronic Circuit
Application: 11/555,603 →
Ate Architecture and Method for Dft Oriented Testing
Application: 11/589,465 →
Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies
Application: 11/552,110 →
Diagnostic Information Capture from Memory Devices with Built-in Self Test
Application: 11/535,974 →
Automatic Test Equipment Receiving Diagnostic Information from Devices with Built-in Self Test
Application: 11/535,909 →
Diagnostic Information Capture from Logic Devices with Built-in Self Test
Application: 11/535,973 →
Wafer Test Head Architecture and Method of Use
Application: 11/525,731 →
Electrical Test Circuit with Active-Load and Output Sampling Capability
Application: 11/534,082 →
Method and an Apparatus for Measuring the Input Threshold Level of Device Under Test
Application: 11/518,766 →
Electrical Coupling Apparatus and Method
Application: 11/460,277 →
Digital to Analog Conversion Using Summation of Multiple Dacs
Application: 11/489,431 →
Method and System for Digital to Analog Conversion Using Multi-Purpose Current Summation
Application: 11/489,190 →
Source Synchronous Timing Extraction, Cyclization and Sampling
Application: 11/481,593 →
Methods for Sampling Equipment and Fluid Conditions
Application: 11/447,646 →