Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test
View Patent ↗In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.
1. Apparatus for testing at least one device under test (DUT), the apparatus comprising:
a tester input/output (I/O) node;
a plurality of DUT I/O nodes;
a plurality of remote pin electronics blocks, each of the remote pin electronics blocks providing a first test function, and each of the remote pin electronics blocks being coupled between the tester I/O node and a respective one of the DUT I/O nodes;
a bypass circuit coupled between the tester I/O node and each of the plurality of DUT I/O nodes, the bypass circuit providing signal bypass paths between the tester I/O node and respective ones of the plurality of DUT I/O nodes, and each of the signal bypass paths bypassing the first test function provided by a respective one of the remote pin electronics blocks; and
a control system configured to enable and disable the bypass circuit and enable one of the signal bypass paths at a time.
2. The apparatus of claim 1 , further comprising:
a tester pin electronics block providing a second test function; and
a signal path coupling the tester I/O node to the tester pin electronics block.
3. The apparatus of claim 2 , further comprising an integrated circuit in which the remote pin electronics blocks and bypass circuit, but not the tester pin electronics block, are integrated.
4. The apparatus of claim 2 , wherein the signal path comprises a transmission line.
5. The apparatus of claim 2 , wherein signal paths coupling the remote pin electronics blocks to the respective ones of the DUT I/O nodes are shorter than signal paths coupling the tester pin electronics block to the DUT I/O nodes, wherein the signal paths coupling the tester pin electronics block to the DUT I/O nodes pass through the bypass circuit.
6. The apparatus of claim 2 , wherein the first test function and the second test function are the same test function.
7. The apparatus of claim 2 , wherein the first test function differs from the second test function.
8. The apparatus of claim 1 , wherein each of the remote pin electronics blocks comprises a comparator, each comparator having a first input that receives a signal from a respective one of the DUT I/O nodes, a second input that receives a baseline signal, and an output that is coupled to the tester I/O node.
9. The apparatus of claim 1 , wherein the bypass circuit provides bidirectional signal paths between the tester I/O node and the DUT I/O nodes.
10. The apparatus of claim 1 , further comprising an integrated circuit in which the remote pin electronics blocks and bypass circuit are integrated.