Patent Assignment
Reel/Frame 035371/0265
Assignment of Assignor's Interest
Recorded: 2015-04-06
Pages: 25
Assignor
ADVANTEST (SINGAPORE) PTE. LTD.
Executed: 2015-04-01
Assignee
ADVANTEST CORPORATION
SHIN-MARUNOUCHI CENTER BUILDING, 1-6-2 MARUNOUCHI, CHIYODA-KU, TOKYO, 100-0005, JAPAN
Covered Properties
(248)
Powerfail Durable Nvram Testing
Patent:
5,553,238 →
Application:
08/376,322 →
Electrical Connection Structure
Patent:
5,597,982 →
Application:
08/398,345 →
Timing Adjustment Circuit
Patent:
5,589,788 →
Application:
08/435,877 →
A Pin Array Set-Up Device
Patent:
5,834,838 →
Application:
08/767,446 →
Electronic Circuit or Board Tester with Compressed Data-Sequences
Patent:
5,899,961 →
Application:
08/811,153 →
Testing Unit with Testing Information Divided into Redundancy-Free Information and Redundancy Information
Patent:
6,065,144 →
Application:
09/042,442 →
Multi-Channel Architecture with Channel Independent Clock Signals
Patent:
6,055,644 →
Application:
09/050,289 →
Permanent Failure Monitoring in Complex Systems
Patent:
6,216,243 →
Application:
09/050,505 →
Online Documentation and Help System for Computer-Based Systems
Patent:
6,208,338 →
Application:
09/079,985 →
Compressible Elastomeric Contact and Mechanical Assembly Therewith
Patent:
6,183,272 →
Application:
09/093,485 →
Memory Latency Compensation
Optimized Memory Organization in a Multi-Channel Architecture
Patent:
6,304,947 →
Application:
09/140,427 →
Scan Path Test Support
Patent:
6,484,280 →
Application:
09/409,936 →
Output Amplitude Control Circuit
Patent:
6,246,279 →
Application:
09/428,612 →
Attenuation Equailizer for Transmission lines
Patent:
6,239,667 →
Application:
09/526,916 →
Method and Apparatus for Administering Inversion Property in a Memory Tester
Patent:
6,973,404 →
Application:
09/659,198 →
Method and Apparatus for No-Latency Conditional Branching
Patent:
6,968,545 →
Application:
09/659,256 →
Method and Apparatus for Executing a Program Using Primary, Secondary, and Tertiary Memories
Patent:
6,598,112 →
Application:
09/659,259 →
Method and Apparatus for Inserting Programmable Latency Between Address and Data Information in a Memory Tester
Patent:
6,591,385 →
Application:
09/659,539 →
Memory Tester Has Memory Sets Configurable for Use as Error Catch Ram, Tag Ram's, Buffer Memories and Stimulus Log Ram
Patent:
6,851,076 →
Application:
09/672,650 →
Memory Tester Tests Multiple Dut's Per Test Site
Patent:
6,671,844 →
Application:
09/677,202 →
Apparatus and Method for Storing Information During a Test Program
Patent:
6,687,855 →
Application:
09/693,218 →
Memory Tester Omits Programming of Addresses in Detected Bad Columns
Patent:
6,748,562 →
Application:
09/702,578 →
Memory Tester with Enhanced Post Decode
Patent:
6,687,861 →
Application:
09/702,631 →
Test Vector Compression Method
Digital Signal Transition Splitting Method and Apparatus
Algorithmically Programmable Memory Tester with Breakpoint Trigger, Error Jamming and 'Scope Mode That Memorizes Target Sequences
Algorithmically Programmable Memory Tester with History Fifo's That Aid in Error Analysis and Recovery
Integrated Circuit Tester with Multi-Port Testing Functionality
Method and Apparatus for Testing Digital Devices Using Transition Timestamps
Analog to Digital Signal Conversion Method and Apparatus
Patent:
6,462,693 →
Application:
09/875,848 →
Algorithmically Programmable Memory Tester with Test Sites Operating in a Slave Mode
Method and Apparatus for Analog to Digital Conversion Using Time-Varying Reference Signal
Patent:
6,429,799 →
Application:
09/905,747 →
Methods and Apparatus for Minimizing Current Surges During Integrated Circuit Testing
Bandwidth Matching for Scan Architectures in an Integrated Circuit
Circuit for Providing a Logical Output Signal in Accordance with Crossing Points of Differential Signals
Filter for Injecting Data Dependent Jitter and Level Noise
Automatic Test Equipment for Testing a Device Under Test
Virtualized Generic Equipment Model Data and Control Router for Factory Automation
N-Squared Algorithm for Optimizing Correlated Events
High-Sensitivity Differential Data Latch System
Apparatus for Testing Integrated Circuits Having an Integrated Unit for Testing Digital and Analog Signals
Unified Apparatus and Method to Assure Probe Card-to-Wafer Parallelism in Semiconductor Automatic Wafer Test, Probe Card Measurement Systems, and Probe Card Manufacturing
Device, Method, and System for Detecting the Presence of Liquid in Proximity to Electronic Components
Cooler for Electrical and/ or Electronic Components, Linked to Present Cooling Needs
Device Power Supply and Ic Test Apparatus
System and Method for Testing Circuitry on a Wafer
System for Dynamic Re-Allocation of Test Pattern Data for Parallel and Serial Test Data Patterns
Patent:
7,032,145 →
Application:
10/173,199 →
High Output Amplifier for Stable Operation
Plug-Type Connector for Simultaneously Connecting Several Coaxial Cables
Reconstruction of Non-Deterministic Algorithmic Tester Stimulus Used as Input to a Device Under Test
Dynamically Reconfigurable Precision Signal Delay Test System for Automatic Test Equipment
Patent:
6,880,137 →
Application:
10/210,976 →
Droop Compensation Filter Having High Pass Characteristic
Modular Interface Between Test and Application Equipment
System and Method for Heterogeneous Multi-Site Testing
Empirical Data Based Test Optimization Method
Signal Preconditioning for Analog-to-Digital Conversion with Timestamps
Measuring and/or Calibrating a Test Head
Calibration Method for Interleaving an a/D Converter
Electrical System Like a Testing System for Testing the Channels of a Communication System
System and Method for Testing Circuitry Using an Externally Generated Signature
Systems and Methods for Injection of Test Jitter in Data Bit-Streams
Cooling a Microchip on a Circuit Board
Apparatus for Calibrating High Frequency Signal Measurement Equipment
Systems and Methods for Testing Performance of an Electronic Device
Method and Apparatus of Producing Uniform Isotropic Stresses in a Sputtered Film
Operational Amplifier Selecting One of Inputs, and an Amplifying Apparatus Using the Op Amplifier the Verification Method
Digitally Controlled Modular Power Supply for Automated Test Equipment
Patent:
6,900,621 →
Application:
10/613,848 →
Systems and Methods for Testing a Device-Under-Test
Modeling an Electronic Device
Method and System for Automatically Determining a Testing Order When Executing a Test Flow
Patent:
7,047,463 →
Application:
10/642,000 →
Transition Tracking
Digital Measurements of Spread Spectrum Clocking
Cost Estimation for Device Testing
Memory Tester Uses Arbitrary Dynamic Mappings to Serialize Vectors into Transmitted Sub-Vectors and De-Serialize Received Sub-Vectors into Vectors
Methods and Apparatus for Optimizing Lists of Waveforms
Device Testing Control
Circuit and Method for Determining Integrated Circuit Propagation Delay
Systems and Methods for Adaptively Compressing Test Data
Instrument Rack with Direct Exhaustion
Dynamically Reconfigurable Precision Signal Delay Test System for Automatic Test Equipment
Patent:
7,013,417 →
Application:
10/754,968 →
Polynomial Fit for Jitter Separation
Dynamic Waveform Resource Management
Wireless No-Touch Testing of Integrated Circuits
Apparatus for Testing Integrated Circuits Having an Integrated Unit for Testing Digital and Analog Signals
Multiple Clocks with Superperiod
Printed Circuit Board with Improved Cooling of Electrical Component
Verification of Integrated Circuit Tests Using Test Simulation and Integrated Circuit Simulation with Simulated Failure
Parameterized Signal Conditioning
Report Format Editor for Circuit Test
Systems and Methods for Processing Automatically Generated Test Patterns
Provisioning and Use of Security Tokens to Enable Automated Test Equipment
Apparatus, System and/or Method for Converting a Serial Test to a Parallel Test
Apparatus, System and/or Method for Combining Multiple Tests to a Single Test in a Multiple Independent Port Test Environment
Transfer Clocks for a Multi-Channel Architecture
Sigma-Delta Modulator with Pwm Output
Coaxial Dc Block
Programmable Precision Current Controlling Apparatus
Patent:
6,859,157 →
Application:
10/859,642 →
An Electrical Test Circuit with an Active-Load and an Output Sampling Capability
Parallel Calibration System for a Test Device
Sequencer Unit with Instruction Buffering
Method and Apparatus for Electromagnetic Interference Shielding in an Automated Test System
Signal Isolating Blindmate Connector
Patent:
6,981,889 →
Application:
10/903,271 →
Channel with Domain Crossing
Low Distortion Variable Gain and Rooting Amplifier with Solid State Relay
Construction and Use of Dielectric Plate for Mating Test Equipment to a Load Board of a Circuit Tester
Enhanced Stress Metal Spring Contactor
Calibration Method of Time Measurement Apparatus
Methods and Apparatus for Providing Scan Patterns to an Electronic Device
Methods and Apparatus for Programming and Operating Automated Test Equipment
Phase Locked Time Interval Analyzer
Patent:
6,975,106 →
Application:
10/966,229 →
Application of Paging to a Dataset, Graphical Display Window and Graphical Scrollbar Grip
System, Method and Apparatus for Providing Ground Separation Between Different Environments
Mock Wafer, System Calibrated Using Mock Wafer, and Method for Calibrating Automated Test Equipment
Method and Apparatus for Generating a Phase-Locked Output Signal
Method and Apparatus for Variable Sigma-Delta Modulation
Systems and Methods of Allocating Device Testing Resources to Sites of a Probe Card
Method for Optimizing Test Order, and Machine-Readable Media Storing Sequences of Instructions to Perform Same
Patent:
7,050,922 →
Application:
11/036,574 →
Incremental Generation of Calibration Factors for Automated Test Equipment
Clamp and Method for Operating Same
Method and Apparatus for Quantifying the Timing Error Induced by Crosstalk Between Signal Paths
Method and Apparatus for Quantifying the Timing Error Induced by an Impedance Variation of a Signal Path
Digitally Controlled Modular Power Supply for Automated Test Equipment
Patent:
7,154,253 →
Application:
11/087,157 →
Compilation of Calibration Information for Plural Testflows
Device for Releasable Connecting an Interface with a Test Equipment
Model Based Testing for Electronic Devices
Fluid Sampling Device, Tubular Sampling Coupon, and System and Method for Sampling Equipment and Fluid Conditions
Pin Coupler for an Integrated Circuit Tester
Using a Leaf Spring to Attach Clamp Plates with a Heat Sink to Both Sides of a Component Mounted on a Printed Circuit Assembly
Channel Switching Circuit
Power Amplifying Apparatus
Precision Pulse Placement to Form a Binary Pulse Signal
Method and System for Per-Pin Clock Synthesis of an Electronic Device Under Test
Fast Synchronization of a Number of Digital Clocks
Analog Signal Generation Using a Delta-Sigma Modulator
Self Contained, Liquid to Air Cooled, Memory Test Engineering Workstation
Source Synchronous Sampling
Carousel Device, System and Method for Electronic Circuit Tester
Zero Insertion Force Printed Circuit Assembly Connector System and Method
Patent:
7,147,499 →
Application:
11/253,446 →
Method and Apparatus for Eliminating Automated Testing Equipment Index Time
Resource Matrix, System, and Method for Operating Same
System-On-A-Chip Pipeline Tester and Method
Pin Connector
Estimating Boundaries of Schmoo Plots
Error Detection in Compressed Data
Apparatus for Storing and Formatting Data
Method and Machine-Readable Media for Inferring Relationships Between Test Results
Methods and Apparatus Using a Service to Launch and/or Monitor Data Formatting Processes
Methods and Systems for Derivation of Missing Data Objects from Test Data
Method and System for Selectively Processing Test Data Using Subscriptions in a Multi-Formatter Architecture
Systems and Methods for Accumulation of Summaries of Test Data
System, Method and Apparatus for Completing the Generation of Test Records After an Abort Event
Excitation Signal Generator for Improved Accuracy of Model-Based Testing
Testing a Device Under Test by Sampling Its Clock and Data Signal
Asynchronous Digital Data Capture
Self-Repair System and Method for Providing Resource Failure Tolerance
Test System and Method for Testing Electronic Devices Using a Pipelined Testing Architecture
Memory Device Fail Summary Data Reduction for Improved Redundancy Analysis
Method and Apparatus for Determining Which Timing Sets to Pre-Load into the Pin Electronics of a Circuit Test System, and for Pre-Loading or Storing Said Timing Sets
Pin Electronic for Automatic Testing of Integrated Circuits
Memory Device Fail Summary Data Reduction for Improved Redundancy Analysis
Test Device with Test Parameter Adaptation
Calibration Apparatus and Method Using Pulse for Frequency, Phase, and Delay Characteristic
Analog to Digital Conversion Method Using Track/Hold Circuit and Time Interval Analyzer, and an Apparatus Using the Method
Systems, Methods and Apparatus for Synthesizing State Events for a Test Data Stream
Apparatus, Systems and Methods for Processing Signals Between a Tester and a Plurality of Devices Under Test at High Temperatures and with Single Touchdown of a Probe Array
Graphically Extensible, Hardware Independent Method to Inspect and Modify State of Test Equipment
Re-Configurable Architecture for Automated Test Equipment
Mapping Logic for Controlling Loading of the Select Ram of an Error Data Crossbar Multiplexer
Method and Apparatus for a Paddle Board Probe Card
Method for Adjusting Signal Generator and Signal Generator
Methods for Sampling Equipment and Fluid Conditions
Electrical Coupling Apparatus and Method
Source Synchronous Timing Extraction, Cyclization and Sampling
Method and System for Digital to Analog Conversion Using Multi-Purpose Current Summation
Digital to Analog Conversion Using Summation of Multiple Dacs
Method and an Apparatus for Measuring the Input Threshold Level of Device Under Test
Wafer Test Head Architecture and Method of Use
Electrical Test Circuit with Active-Load and Output Sampling Capability
Diagnostic Information Capture from Logic Devices with Built-in Self Test
System and Method for Device Performance Characterization in Physical and Logical Domains with Ac Scan Testing
Process for Improving Design Limited Yield by Efficiently Capturing and Storing Production Test Data for Analysis Using Checksums, Hash Values, or Digital Fault Signatures
Ate Architecture and Method for Dft Oriented Testing
System and Method for Frequency Offset Testing
Method of Manufacturing a Pcb Having Improved Cooling
Process for Identifying the Location of a Break in a Scan Chain in Real Time
Interconnect Assemblies, and Methods of Forming Interconnects, Between Conductive Contact Bumps and Conductive Contact Pads
Liquid Cooled Dut Card Interface for Wafer Sort Probing
Forced Air Cooling of Components on a Probecard
Method and Apparatus for Improving Load Time for Automated Test Equipment
Automated Loader for Removing and Inserting Removable Devices to Improve Load Time for Automated Test Equipment
Evaluation of an Output Signal of a Device Under Test
Apparatus for Locating a Defect in a Scan Chain While Testing Digital Logic
Process for Improving Design-Limited Yield by Localizing Potential Faults from Production Test Data
Methods and Apparatus for Testing a Circuit
Solid High Aspect Ratio via Hole Used for Burn-in Boards, Wafer Sort Probe Cards, and Package Test Load Boards with Electronic Circuitry
High Voltage, High Frequency, High Reliability, High Density, High Temperature Automated Test Equipment (Ate) Switch Design
Patent:
7,348,791 →
Application:
11/685,873 →
System. Method and Apparatus Using at Least One Flex Circuit to Connect a Printed Circuit Board and a Socket Card Assembly That Are Oriented at a Right Angle to One Another
High Impedance, High Parallelism, High Temperature Memory Test System Architecture
Feature-Oriented Test Program Development and Execution
System and Method for Electronic Testing of Multiple Memory Devices
Clamp and Method for Operating Same
Method and Apparatus for Displaying Test Data
Resource Access Manager for Controlling Access to a Limited-Access Resource
Method for Operating a Secure Semiconductor Ip Server to Support Failure Analysis
Error Catch Ram Support Using Fan-Out/Fan-in Matrix
Communication Circuit for a Bi-Directional Data Transmission
Locating Hold Time Violations in Scan Chains by Generating Patterns on Ate
Dynamic Mask Memory for Serial Scan Testing
Tester, Method for Testing a Device Under Test and Computer Program
System and Method for Electronic Testing of Devices
System and Method for Simulating a Semiconductor Wafer Prober and a Class Memory Test Handler
Screw-Less Latching System for Securing Load Boards
System and Method for Baseband Calibration
Parallel Test Circuit with Active Devices
Patent:
8,384,410 →
Application:
12/035,378 →
Methods for Analyzing Scan Chains, and for Determining Numbers or Locations of Hold Time Faults in Scan Chains
Methods and Apparatus for Estimating a Position of a Stuck-at Defect in a Scan Chain of a Device Under Test
Apparatus, Method, and Computer Program for Obtaining a Time-Domain-Reflection Response-Information
Multi-Stage Data Processor with Signal Repeater
A Method of Fabricating a Probe Card Assembly Using Magnetically Aligned Electrical Contact Elements, a Stamped Construction Electrical Contact Element Usable with the Method, and a Standalone Probe Card Tester Formable Using the Method
Massively Parallel Interface for Electronic Circuit
Time-To-Digital Conversion with Calibration Pulse Injection
Methods and Apparatus That Selectively Use or Bypass a Remote Pin Electronics Block to Test at Least One Device Under Test
Transmit/Receive Unit, and Methods and Apparatus for Transmitting Signals Between Transmit/Receive Units
Time-To-Digital Conversion with Delay Contribution Determination of Delay Elements
Calibrating Signals by Time Adjustment
Decorrelation of Data by Using This Data
Format Transformation of Test Data
Asynchronous Sigma-Delta Digital-Analog Converter
Test Module with Blocks of Universal and Specific Resources
Method and Product for Testing a Device Under Test
Method and Apparatus for Determining a Minimum/Maximum of a Plurality of Binary Values
Methods, Apparatus and Articles of Manufacture for Testing a Plurality of Singulated Die
Test Electronics to Device Under Test Interfaces, and Methods and Apparatus Using Same
Method and Apparatus for Determining Relevance Values for a Detection of a Fault on a Chip and for Determining a Fault Probability of a Location on a Chip
System, Method and Computer Program for Detecting an Electrostatic Discharge Event
Chip Tester, Method for Providing Timing Information, Test Fixture Set, Apparatus for Post-Processing Propagation Delay Information, Method for Post-Processing Delay Information, Chip Test Set Up and Method for Testing Devices Under Test
Test System and Method for Testing Electronic Devices Using a Pipelined Testing Architecture
Methods for Fabricating Circuit Boards
High Impedance, High Parallelism, High Temperature Memory Test System Architecture
Method of Sharing a Test Resource at a Plurality of Test Sites, Automated Test Equipment, Handler for Loading and Unloading Devices to Be Tested and Test System
Method and Apparatus for the Determination of a Repetitive Bit Value Pattern
Apparatus and Method for Estimating Data Relating to a Time Difference and Apparatus and Method for Calibrating a Delay Line
Data Processing Unit and a Method of Processing Data
Signal Distribution Structure and Method for Distributing a Signal
State Machine and Generator for Generating a Description of a State Machine Feedback Function
Re-Configurable Test Circuit, Method for Operating an Automated Test Equipment, Apparatus, Method and Computer Program for Setting Up an Automated Test Equipment
System and Method for Electronic Testing of Partially Processed Devices
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.
Corrective Assignment to Correct the Assignee Address Previously Recorded at Reel: 035371 Frame: 0265. Assignor(S) Hereby Confirms the Assignment.
Apr 14, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035425/0768 →
Change of Address
Dec 18, 2018
From: ADVANTEST CORPORATION
To: ADVANTEST CORPORATION
Reel/Frame 047987/0626 →