System and method for testing circuitry on a wafer
View Patent ↗A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.
1. A system for testing a plurality of dice on a semiconductor wafer, said system comprising:
a communication system included on said semiconductor wafer, said communication system interconnecting a plurality of dice on said semiconductor wafer for communicating test data from at least one of said plurality of dice to at least one other of said plurality of dice, said test data including error data outputted from one of said plurality of dice; and
wherein at least a portion of said system for testing a plurality of dice is implemented on a dedicated die for testing said plurality of dice, wherein said at least a portion of said system implemented on said dedicated die comprises a data processing system for processing test data for at least one of said plurality of dice.
2. The system of claim 1 further comprising:
at least one access pad for receiving input test data for said plurality of dice.
3. The system of claim 2 wherein said at least one access pad for receiving input test data is a die pad included in one of said plurality of dice.
4. The system of claim 1 further comprising:
at least one access pad for receiving output test data generated by said plurality of dice responsive to said input test data.
5. The system of claim 4 wherein said at least one access pad for receiving output test data is a die pad included in one of said plurality of dice.
6. The system of claim 1 wherein said data processing system comprises at least one selected from the group consisting of:
compression circuitry, decompression circuitry, die signature analyzer circuitry, comparator circuitry, PMU circuitry, FPGA circuitry, MPU circuitry, and built-in self test (BIST) circuitry.
7. The system of claim 1 wherein said data processing system comprises comparator circuitry for comparing output test data generated by at least one of said plurality of dice responsive input test data input to said at least one of said plurality of dice with expected output data for said at least one of said plurality of dice.
8. The system of claim 1 wherein said data processing system is implemented on at least one of said plurality of dice.
9. The system of claim 1 wherein at least a portion of said system for testing a plurality of dice is implemented on otherwise unused semiconductor wafer area.
10. The system of claim 1 wherein a portion of multiple dice is utilized to implement at least a portion of said system for testing a plurality of dice.
11. The system of claim 1 wherein said communication system implements an input scheme for inputting test data to said plurality of dice, wherein said input scheme is selected from the group consisting of:
broadcasting, pipelining external to said dice, and pipelining internal to said dice.
12. The system of claim 1 wherein said communication system implements an output scheme for outputting test data from said plurality of dice, wherein said output test scheme is selected from the group consisting of:
broadcasting using a comparator, pipelining external to said dice, pipelining internal to said dice, signature with broadcasting using a comparator, and signature with pipelining.
13. The system of claim 1 wherein said data processing system on said dedicated die is configured to compare said error data with an expected data value for at least one of said plurality of dice.
14. A method for testing a plurality of dice on a semiconductor wafer, said method comprising:
receiving test data at a semiconductor wafer having a plurality of dice fabricated thereon, wherein said receiving comprises receiving said test data from a test system implemented on at least one dedicated die of said semiconductor wafer; and
communicating said test data to multiple of said plurality of dice concurrently via a communication system fabricated on said semiconductor wafer that interconnects said multiple dice, wherein at least a portion of said test data is output test data responsive to input test data and is communicated from an output of at least one of said multiple dice to an input of at least one other of said multiple dice.
15. The method of claim 14 wherein said receiving step comprises:
receiving said test data via at least one access pad on said semiconductor wafer.
16. The method of claim 15 wherein said at least one access pad is a die pad included in one of said multiple dice.
17. The method of claim 14 wherein said receiving step comprises:
receiving said test data from a test system that is external to said semiconductor wafer.
18. The method of claim 14 further comprising:
generating output data for each of said multiple dice responsive to said received test data communicated thereto.
19. The method of claim 18 further comprising:
communicating said output data from at least one of said multiple dice to at least one other of said multiple dice.
20. The method of claim 18 wherein said generating said output data comprises using comparator circuitry on said semiconductor wafer for comparing output data generated by at least one of said multiple dice with expected output data for said at least one of said multiple dice.
21. A system for testing a plurality of dice on a semiconductor wafer, said system comprising:
circuitry fabricated on a semiconductor wafer, wherein said circuitry is defined by a repeatable reticle pattern and wherein said circuitry comprises a communication system interconnecting a plurality of dice on said semiconductor wafer for concurrently communicating test data to said plurality of dice, wherein said communication system interconnects said plurality of dice to communicate test data which is outputted from at least one of said plurality of dice and is inputted to at least one other of said plurality of dice.
22. The system of claim 21 wherein said circuitry further comprises:
a data processing system for processing test data for at least one of said plurality of dice.
23. The system of claim 22 wherein said data processing system comprises at least one selected from the group consisting of
compression circuitry, decompression circuitry, die signature analyzer circuitry, comparator circuitry, PMU circuitry, FPGA circuitry, MPU circuitry, and built-in self test (BIST) circuitry.
24. The system of claim 22 wherein said data processing system comprises comparator circuitry for comparing output test data generated by at least one of said plurality of dice responsive input test data input to said at least one of said plurality of dice with expected output data for said at least one of said plurality of dice.
25. The system of claim 22 wherein said data processing system is implemented on at least one of said plurality of dice.
26. The system of claim 21 further comprising:
at least a portion of said system for testing a plurality of dice is implemented on a dedicated die of said semiconductor wafer for testing said plurality of dice.