IP Library Granted Patent US 8,005,633
Granted Patent B2
US 8,005,633 · App. 11/347,888 · Granted Aug 23, 2011

Excitation signal generator for improved accuracy of model-based testing

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Quick Facts
Patent No.
US 8,005,633
App. No.
11/347,888
Granted
Aug 23, 2011
Kind
B2
Abstract

An excitation signal generator (“ESG”) is described. The ESG generates an minimized excitation signal for use in a test system to generate a functional model of a device under test (“DUT”) where extreme values of the minimized excitation signal are increased toward a central value without changing the power spectrum at the DUT.

Claims (43)

1. A method for generation of a minimized excitation signal with an associated power spectrum, the method comprising:

determining a frequency range of a system under test (“SUT”);

identifying a number of frequency lines to be in the minimized excitation signal;

computing a set of frequency lines based on the frequency range of the SUT and the number of frequency lines;

identifying a minimum amplitude of a frequency line in the set of frequency lines; and

generating the minimized excitation signal having extreme values in response to receipt of an input signal, wherein generating the minimized excitation signal includes

generating the minimized excitation signal having the extreme values using the number of frequency lines, frequency range of the SUT and the minimum amplitude; and

utilizing crest factor minimization to increase the extreme values of the minimized excitation signal toward a central value, without affecting the power spectrum of the minimized excitation signal.

2. The method of claim 1 , wherein generating the minimized excitation signal further includes shifting the minimized excitation signal so that the minimized excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

3. The method of claim 2 , wherein generating the minimized excitation signal further includes scaling the minimized excitation signal so that the minimized excitation signal uses a fill signal range of the DUT.

4. The method of claim 1 , wherein generating the minimized excitation signal further includes scaling the minimized excitation signal so that the minimized excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

5. The method of claim 4 , wherein the DUT is an amplifier.

6. The method of claim 1 , further includes generating the input signal with a signal generator from which the minimized excitation signal is generated.

7. The method of claim 6 , wherein generating the input signal and the minimized excitation signal occurs within a single device within the SUT.

8. An excitation signal generator (“ESG”) with an input for receipt of an input signal, wherein the ESG is configured to generate a minimized excitation signal with an associated power spectrum, the ESG comprising:

a second input configured to receive a frequency range associated with a system under test (“SUT”); and

a controller in signal communication with the input and second input, the controller configured to

determine the frequency range of the SUT,

identify a number of frequency lines to be in a minimized excitation signal;

compute a set of frequency lines based on the frequency range of the SUT and the number of frequency lines;

identify a minimum amplitude of a frequency line in the set of frequency lines, and

generate the minimum excitation signal having extreme values in response to receipt of the input signal, wherein configured to generate minimum excitation signal includes

the minimized excitation signal having the extreme values using the number of frequency lines, frequency range of the SUT, and minimum amplitude; and

utilizing crest factor minimization to increase the extreme values of the minimized excitation signal toward a central value, without affecting the power spectrum of the minimized excitation signal.

9. The ESG of claim 8 , wherein the controller is further configured to shift the input signal such that the minimize excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

10. The ESG of claim 9 , wherein the controller is fiber configured to scale the input signal so that the minimized excitation signal uses the full signal range of the DUT in the SUT.

11. The ESG of claim 8 , wherein the controller is further configured to scale the input signal so that the minimized excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

12. The ESG of claim wherein the OUT is an amplifier.

13. The ESG of claim 8 , further includes a signal generator that is configured to generate the input signal that is input into the ESG.

14. The ESG of claim 13 , wherein the ESG is a single device.

15. A non-transitory computer readable media having computer instructions stored thereon for causing a computer processor to generate a minimized excitation signal with an associated power spectrum, the computer readable media comprising:

a first set of instructions for determining a frequency range of a system under test (“SUT”);

a second set of instructions for identifying a number of frequency lines to be in the minimized excitation signal;

a third set of instructions for computing a set of frequency lines based on the frequency range of the SUT and the number of frequency lines;

a fourth set of instructions for identifying a minimum amplitude of a frequency line in the set of frequency lines; and

a fifth set of instructions for generating the minimized excitation signal having extreme values in response to receipt of an input signal, wherein generating the minimized excitation signal includes

generating the minimized excitation signal having the extreme values using the number of frequency lines, frequency range of the SUT, and the minimum amplitude; and

utilizing crest factor minimization to increase the extreme values of the minimized excitation signal toward a central value, without affecting the power spectrum of the minimized excitation signal.

16. The non-transitory computer readable media of claim 15 , wherein the fifth set of instructions for generating the minimized excitation signal further includes a sixth set of instructions for shifting the input signal such that the minimized excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

17. The non-transitory computer readable media of claim 16 , wherein the fifth set of instructions for generating the minimized excitation signal further includes a seventh set of instructions for scaling the input signal such that the minimized excitation signal uses a full signal range of the DUT in the SUT.

18. The non-transitory computer readable media of claim 15 , wherein the fifth set of instructions for generating the minimized excitation signal further includes a sixth set of instructions for scaling the input signal such that the minimized excitation signal uses a full signal range of a device under test (“DUT”) in the SUT.

19. The non-transitory computer readable media of claim 18 , wherein the sixth set of instructions for scaling utilizes a full signal range of an amplifier.

20. The non-transitory computer readable media of claim 15 , wherein the fifth set of instructions for generating the minimized excitation signal further includes instructions for generating the input signal with a signal generator from which the minimized excitation signal is generated.

Assignments (6)
CHANGE OF ADDRESS Recorded Dec 18, 2018
From: ADVANTEST CORPORATION
To: ADVANTEST CORPORATION
Reel/Frame 047987/0626 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 035371 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 14, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035425/0768 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035371/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2012
From: VERIGY (SINGAPORE) PTE LTD
To: ADVANTEST (SINGAPORE) PTE LTD
Reel/Frame 027896/0018 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2007
From: AGILENT TECHNOLOGIES, INC.
To: VERIGY (SINGAPORE) PTE. LTD.
Reel/Frame 019015/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2006
From: BARFORD, LEE ALTON; TUFILLARO, NICHOLAS; KHOCHE, AJAY
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 017818/0350 →