Method and system for per-pin clock synthesis of an electronic device under test

1. A method for synthesizing a plurality of digital clock signals to be applied to respective pins of an electronic device under test comprising a plurality of pins, said method comprising:

generating a reference clock by a central clock generator;

providing said reference clock from said central clock generator to a plurality of electronic circuits, each of said plurality of electronic circuits comprising a test signal processor, each of said test signal processors controlling at least one pin of said device under test for providing a stimulus in accordance with a predetermined signal pattern and for receiving a response to the stimulus; and

on the basis of said reference clock, generating at the test signal processor a local digital clock signal, and providing said local digital clock signal to said pin of said device under test controlled by said test signal processor,

wherein generating said local digital clock signal comprises modulating at the test signal processor the frequency, phase and/or amplitude of said local digital clock signal for said pin of said device under test controlled by said test signal processor according to digital data stored in a digital data source.

2. The method of claim 1 , wherein means for generating said local digital clock signal are monolithically integrated in said test signal processor, such that timing and clock of said signal pattern is generated for each pin in one semiconductor chip.

3. The method of claim 2 , wherein at least for some of said pins, an individual test signal processor is provided with integrated means for generating said local digital clock signal.

4. The method of claim 3 , wherein for all pins of said device under test, an individual test signal processor is provided with integrated means for generating said local digital clock signal.

5. The method of claim 1 , comprising a N/M multiplication of said reference clock, with N and M being integer with N<M, wherein said N/M multiplication of said reference clock is performed by a phase locked loop.

6. The method of claim 5 , comprising

synchronizing said N/M multiplied reference clock with a synchronizing signal generated centrally by a N/M multiplication of said reference clock by the phase locked loop, wherein N and M are integer with N<M, and

providing said synchronizing signal to said plurality of electronic circuits.

7. The method of claim 1 , wherein a super-period is generated centrally and distributed to said electronic circuits, said super-period is set to lowest common multiple of all clock periods of the local digital clock signals that need to be synchronized.

8. The method of claim 7 , wherein said local digital clock signal is synchronized to said super-period.

9. The method of claim 7 , wherein said super-period is generated from said reference clock by N/M multiplication, wherein N and M are integers with N<M.

10. The method of claim 9 , wherein said local digital clock signal is synchronized to said super-period.

11. A software program or product, stored on a data carrier, for executing the method of claim 1 when running on a data processing system.

12. The method of claim 11 , wherein the data processing system is a computer.

13. A system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said system comprising

means for generating a reference clock by a central clock generator;

means for providing said reference clock from said central clock generator to a plurality of electronic circuits, each of said plurality of electronic circuits comprising a test signal processor, each of said test signal processors controlling at least one pin of said device under test for providing a stimulus in accordance with a predetermined signal pattern and for receiving a response to the stimulus; and

means for generating at the test signal processor a local digital clock signal on the basis of said reference clock, and for providing said local digital clock signal to said pin of said device under test controlled by said test signal processor,

wherein said means for generating said local digital clock signal comprises means for modulating at the test signal processor the frequency, phase and/or amplitude of said local digital clock signal for said pin of said device under test controlled by said test signal processor according to digital data stored in a digital data source.

14. A method for synthesizing a plurality of digital clock signals to be applied to respective pins of an electronic device under test comprising a plurality of pins, said method comprising:

generating a reference clock by a central clock generator;

providing said reference clock from said central clock generator to a plurality of electronic circuits, each of said plurality of electronic circuits comprising a test signal processor, each of said test signal processors controlling at least one pin of said device under test for providing a stimulus in accordance with a predetermined signal pattern and for receiving a response to the stimulus;

on the basis of said reference clock, generating at the test signal processor a local digital clock signal, and providing said local digital clock signal to said pin of said device under test controlled by said test signal processor, wherein generating said local digital clock signal comprises dividing said reference signal clock signal by M and multiplying said divided reference signal clock signal by N avg using a PLL, with M being an integer and N avg <M; and

synchronizing said N avg /M divided reference clock signal with a synchronizing signal generated centrally by a N/M multiplication of said reference clock by a phase locked loop, wherein N and M are integer with N<M, wherein said synchronizing signal is provided to said plurality of electronic circuits.

15. A system for synthesizing a plurality of digital clock signals to be applied to respective pins of an electronic device under test comprising a plurality of pins, said method comprising:

means for generating a reference clock by a central clock generator;

means for providing said reference clock from said central clock generator to a plurality of electronic circuits, each of said plurality of electronic circuits comprising a test signal processor, each of said test signal processors controlling at least one pin of said device under test for providing a stimulus in accordance with a predetermined signal pattern and for receiving a response to the stimulus;

means for generating at the test signal processor a local digital clock signal on the basis of said reference clock, and for providing said local digital clock signal to said pin of said device under test controlled by said test signal processor, wherein generating said local digital clock signal comprises dividing said reference signal clock signal by M and multiplying said divided reference signal clock signal by N avg using a PLL, with M being an integer and N avg <M; and

means for synchronizing said N avg /M divided reference clock signal with a synchronizing signal generated centrally by a N/M multiplication of said reference clock by a phase locked loop, wherein N and M are integer with N<M, wherein said synchronizing signal is provided to said plurality of electronic circuits.