Sequencer unit with instruction buffering

1. A sequencer unit for generating a stream of test data in a channel of an automated test equipment, said sequencer unit comprising:

a first instruction processing unit for receiving and processing a stream of instructions, wherein in case data is required by a certain instruction, a corresponding data read request for fetching said data is issued;

an instruction buffer for buffering instructions that wait for requested data; and

a second instruction processing unit for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate the stream of test data.

2. The sequencer unit of claim 1 , wherein said first instruction processing unit irequests instructions by issuing instruction read requests.

3. The sequencer unit of claim 1 , wherein said stream of instructions comprises at least one of flow control instructions, data sequencing instructions, break instructions, set data instructions.

4. The sequencer unit of claim 1 , wherein said stream of instructions comprises flow control instructions and said first instruction processing unit processes said flow control instructions.

5. The sequencer unit of claim 1 , wherein said stream of instructions comprises data sequencing instructions, and said first instruction processing unit preprocesses said data sequencing instructions, and wherein said second instruction processing unit completes processing of said data sequencing instructions.

6. The sequencer unit of claim 1 , comprising at least one of the features:

said first instruction processing unit stores instructions that wait for requested data to said instruction buffer;

said second instruction processing unit assigns the requested data in sequential order to the corresponding instructions buffered in the instruction buffer;

said instruction buffer is implemented as a FIFO buffer;

said sequencer unit receives said instructions and said data from at least one storage;

said first instruction processing unit receives said instructions from an instruction memory that is preferably implemented as an SRAM;

said second instruction processing unit receives said requested data from a data memory that is preferably implemented as a DRAM;

said sequencer unit receives both said instructions and said data from a shared memory;

said first instruction processing unit issues data read requests that indicate both the start address and the size of requested data.

7. The sequencer unit of claim 1 , wherein said channel is responsible for at least one of: providing stimulus data to at least one DUT, and receiving response data from said at least one DUT.

8. The sequencer unit of claim 7 , comprising at least one of the features:

said test data includes at least one of vector data and expected data;

said sequencer unit provides said test data to at least one of the channel's drive path and the channel's receive path;

said test data additionally includes set data for modifying the channel's settings;

said test data additionally includes refresh vectors initiates a refresh of at least one DRAM that is part of said at least one DUT.

9. The sequencer unit of claim 1 , wherein said sequencer unit generates test data;

and wherein said sequencer unit is included in at least one channel for use in an automated test equipment, said at least one channel including:

at least one storage for storing at least one of instructions and data; and

a result processing unit for evaluating response data obtained from at least one DUT.

10. The at least one channel of claim 9 , wherein said at least one channel is responsible for at least one of: providing stimulus data to said at least one DUT, and receiving response data from said at least one DUT;

and wherein said at least one channel is included in an automated test equipment for testing at least one DUT, said automated test equipment including a central facility for coordinating said at least one channel.

11. The automated test equipment of claim 10 , comprising one of the features:

said automated test equipment is implemented as a centralized tester architecture that is under clock control of said central facility;

said automated test equipment is implemented according to a tester-per-pin architecture, wherein said channels represent independent functional units.

12. The sequencer unit of claim 6 , wherein said shared memory is implemented as at least one of a DRAM and a RDRAM.