Method and apparatus for generating a phase-locked output signal

1. A method of generating a phase-locked output signal, the method comprising:

generating an intermediate signal phase locked to an input signal, the generating compromising frequency dividing the intermediate signal by a temporally-varying divide ratio sequence to generate a first feedback signal and phase comparing the first feedback signal with the input signal; and

generating the output signal phase locked to the first feedback signal, the generating comprising frequency dividing the output signal by the temporally-varying divide ratio sequence to generate a second feedback signal and phase comparing the second feedback signal with the first feedback signal.

2. The method as claimed in claim 1 , wherein generating the first feedback signal and generating the output signal additionally comprises using Fractional_N phase-locked loops comprising substantially identical components.

3. The method as claimed in claim 1 , wherein:

the method additionally comprises generating a sigma-delta modulated divide ratio sequence as the temporally-varying divide ratio sequence; and

frequency dividing the intermediate signal by the temporally-varying divide ratio sequence and frequency dividing the output signal by the temporally-varying divide ratio sequence are performed in response to the sigma-delta modulated divide ratio sequence.

4. The method as claimed in claim 3 , wherein:

generating a sigma-delta modulated divide ratio sequence as the temporally-varying divide ratio sequence comprises using a sigma-delta modulator of an order higher than a first order sigma-delta modulator.

5. The method as claimed in claim 3 , additionally comprising clocking the sigma-delta modulated divide ratio sequence with the first feedback signal.

6. The method as claimed in claim 1 , wherein:

phase comparing the first feedback signal with the input signal generates a first comparison signal;

generating the intermediate signal additionally comprises:

filtering the first comparison signal to generate a first frequency control signal; and

generating the intermediate signal at a frequency defined by the first frequency control signal;

phase comparing the second feedback signal with the first feedback signal generates a second comparison signal; and

generating the output signal additionally comprises:

filtering the second comparison signal to generate a second frequency control signal; and

generating the output signal at a frequency defined by the second frequency control signal.

7. A Fractional_N phase locked loop, comprising:

a divide ratio sequence generator operable to generate a temporally-varying divide ratio sequence; and

a first phase-locked loop and a second phase-locked loop, each phase-locked loop comprising a phase comparator having a signal input, a feedback input and an output, and additionally comprising a loop filter, a VCO and a frequency divider, the loop filter, the VCO and the frequency divider connected in series between the output and the feedback input of the phase comparator; wherein:

the signal input of one of the phase comparators is directly connected to the feedback input of the other of the phase comparators;

the signal input of the other of the phase comparators is connected to receive an input signal; and

the frequency dividers each have a divide ratio control input connected to the divide ratio sequence generator to receive the temporally-varying divide ratio.

8. The Fractional_N phase-locked loop as claimed in claim 7 , wherein the first phase-locked loop and the second phase-locked loop comprise identical components.

9. The Fractional_N phase-locked loops as claimed in claim 7 , wherein the divide ratio sequence generator comprises a sigma-delta modulator.

10. The Fractional_N phase-locked loop as claimed in claim 9 , wherein the sigma-delta modulator comprises a clock input connected to the feedback input of the other of the phase comparators.

11. The Fractional_N phase-locked loop as claimed in claim 9 , wherein: the sigma-delta modulator comprises an output connected to the divide ratio control input of the frequency dividers.

12. The Fractional_N phase-locked loop as claimed in claim 9 , wherein the sigma-delta modulator is of an order higher than a first order modulator.

13. The Fractional_N phase-locked loop as claimed in claim 9 , wherein the sigma-delta modulator is a third order modulator.

14. A circuit for generating an output signal having a frequency defined by a divide ratio signal, the circuit comprising:

a divide ratio sequence generator connected to receive the divide ratio signal;

a first phase-locked loop and a second phase-locked loop, each phase-locked loop having a phase comparator and a signal input, a feedback input and an output and comprising a frequency divider connected between the output and the feedback input; wherein:

the signal input of one of the phase comparators is directly connected to the feedback input of the other of the phase comparators;

the output of the second phase-locked loop provides the output signal; and

each frequency divider has a divide ratio control input connected to the divide ratio sequence generator.

15. The circuit as claimed in claim 14 , wherein the first phase-locked loop and the second phase-locked loop comprise substantially identical components.

16. The circuit as claimed in claim 14 , wherein the divide ratio sequence generator comprises a sigma-delta modulator.

17. The circuit as claimed in claim 16 , wherein the sigma-delta modulator comprises a clock signal input connected to the feedback input of the first phase-locked loop.

18. The circuit as claimed in claim 16 , wherein the sigma-delta modulator is of an order higher than a first order modulator.

19. The circuit as claimed in claim 16 , wherein the sigma-delta modulator is a third order modulator.

20. The circuit as claimed in claim 14 , wherein:

each phase-locked loop additionally comprises:

a phase comparator providing the signal input and the feedback input of the phase locked loop;

a loop filter connected to the output of the phase comparator; and

a voltage controlled oscillator connected to the output of the loop filter; and

the frequency divider of each phase-locked loop is connected between the output of the voltage-controlled oscillator and the feedback input of the phase comparator.