System and method for testing circuitry using an externally generated signature

1. An off-chip test system comprising:

means for inputting test data to a chip under test;

means for receiving output data from said chip under test responsive to said input test data;

means for generating a signature for at least a portion of said received output data, wherein said received output data is divided into a plurality of windows each comprising a predetermined number of bits and wherein said means for generating a signature generates a signature for each of said plurality of windows;

means for comparing said generated signature with an expected signature; and

means for storing information to an error map log if said generated signature fails to match with said expected signature.

2. The off-chip test system of claim 1 wherein said means for storing information does not require further interaction with said chip under test after determining that said generated signature fails to match said expected signature for acquiring said information to be stored to said error map log.

3. The off-chip test system of claim 1 wherein said means for comparing comprises:

means for comparing said generated signature for a first window with an expected signature for said first window.

4. The off-chip test system of claim 3 wherein said means for storing information comprises:

means for storing information to an error map log about at least said first window, if said generated signature for said first window fails to match with said expected signature for said first window.

5. The off-chip test system of claim 1 wherein said chip under test comprises circuitry on a semiconductor wafer, arid said off-chip test system is arranged external to said wafer.

6. The off-chip test system of claim 1 wherein said chip under test is a packaged chip, and said off-chip test system is arranged external to said packaged wafer.

7. The off-chip test system of claim 1 further comprising:

means for masking at least a portion of said received output data from being used in generating said signature.

8. The off-chip test system of claim 1 further comprising:

means for storing mask data identifying bits of said received output data to be masked, wherein said mask data is compressed.

9. The off-chip test system of claim 8 further comprising:

means for decompressing said mask data.

10. The off-chip test system of claim 8 further comprising:

means for compressing said mask data.

11. The off-chip test system of claim 1 wherein said means for storing information to said error map log stores said at least a portion of said received output data used for generating said signature that fails to match with said expected signature.

12. The system of claim 1 wherein the input test data comprises at least one input test pattern, and wherein the plurality of windows each comprises a predetermined number of output bits that are output responsive to a single input test pattern.

13. The system of claim 1 wherein the input test data comprises a plurality of different input test patterns, and wherein the plurality of windows each comprises a predetermined number of output bits that are output responsive to different input test patterns.

14. A system for testing circuitry, said system comprising:

automated test equipment external to said circuitry that is at least temporarily communicatively coupled to said circuitry, wherein said automated test equipment comprises a communicative interface for inputting test data to said circuitry, a communicative interface for receiving output data from said circuitry responsive to said input test data, logic operable to determine a plurality of windows of the received output data, logic operable to generate a signature for each of the plurality of windows, compare logic for comparing a generated signature with an expected signature, and logic for storing information to an error map log if a generated signature fails to match an expected signature.

15. The system of claim 14 wherein said circuitry comprises circuitry on a semiconductor wafer.

16. The system of claim 14 wherein said logic for storing said information to an error map log does not require further interaction with said circuitry after detection of a generated signature failing to match an expected signature.

17. The system of claim 14 wherein said information stored to an error map log comprises said at least a portion of the received output data used for generating said signature that failed to match the expected signature.

18. The system of claim 14 wherein said automated test equipment further comprises:

logic for masking at least a portion of the received output data from being used is in generating the signature.

19. The system of claim 18 wherein said automated test equipment further comprises:

data storage communicatively coupled thereto that comprises mask data identifying bits of the received output data to be masked, wherein said mask data is compressed.

20. The system of claim 19 wherein said automated test equipment further comprises:

logic for decompressing the mask data.

21. The system of claim 14 further comprising:

logic for determining whether generated signatures fail to match expected signatures for a predetermined number of different windows, wherein said logic for storing information to an error map log performs said storing responsive to the determining logic determining that generated signatures fail to match expected signatures for the predetermined number of different windows.

22. A method for testing circuitry, said method comprising:

inputting test data to circuitry under test;

receiving, at an external test device, output data from said circuitry under test responsive to said input test data;

dividing said received output data into a plurality of windows, each window comprising a predetermined number of bits;

generating, at said external test device, a signature for each of said plurality of windows;

comparing, for each of the windows, said generated signature with an expected signature for the corresponding window to determine whether said circuitry under test functions as expected; and

if said generated signature fails to match with said expected signature, storing information to an error map log, wherein further interaction with said circuitry under test is not required after determining that said generated signature fails to match said expected signature for acquiring said information for storing said information to said error map log.

23. The method of claim 22 wherein said comparing step comprises:

comparing said generated signature for a first window with an expected signature for said first window.

24. The method of claim 23 wherein said storing information to an error map log further comprises:

if said generated signature for said first window fails to match with said expected signature for said first window, storing information about at least said first window to said error map log.

25. The method of claim 24 wherein said information about said first window comprises:

the received output data of said first window.

26. The method of claim 22 further comprising:

generating said expected signature for each of the windows, wherein said generating said expected signatures comprises

determining whether a first window of expected output bits is available for a given test, and

when determined that the expected output bits for the first window are available, inputting the expected output bits for the first window to signature generation logic, wherein the signature generation logic generates an expected signature for the first window based on the expected output bits for the first window.

27. The method of claim 22 further comprising:

receiving, at the external test device, input specifying the predetermined number of bits for at least one of the windows.