Source synchronous timing extraction, cyclization and sampling
View Patent ↗A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.
1. A tester for testing loopback functionality of a device under test (DUT), comprising:
a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT; and
a timing irregularity extraction function that extracts the timing irregularity data from event-based test data intentionally injected with timing irregularities, for injection into the test data by the timing irregularities injection apparatus.
2. The tester of claim 1 , further comprising:
loopback connection means which connect to one or more output drivers of the DUT for receiving the test data generated by the DUT, and which connect to one or more input receivers of the DUT for applying the test data injected with the timing irregularity data to the DUT.
3. The tester of claim 1 , wherein:
said timing irregularity data comprises clock period jitter.
4. The tester of claim 1 , wherein:
said timing irregularities comprise clock period drift.
5. A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT), the DUT comprising one or more output drivers and one or more input receivers and a pattern generator that generates the test patterns which are output onto the one or more output drivers, the method comprising:
obtaining timing irregularities by,
receiving event-based test data containing intentionally injected timing irregularities; and
extracting the timing irregularities from the event-based test data;
receiving the test patterns self-generated by the device under test driven from the one or more output drivers of the DUT;
injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein; and
applying the test patterns with timing irregularities injected therein to the one or more input receivers of the DUT.
6. The method of claim 5 , further comprising:
obtaining test results from the DUT, the test results indicating device operation based on the test patterns with timing irregularities injected therein received by the one or more input receivers of the DUT; and
determining whether the DUT is operating properly based on the test results.
7. The method of claim 5 , wherein:
said timing irregularities comprise clock period jitter.
8. The method of claim 5 , wherein:
said timing irregularities comprise clock period drift.
9. A non-transitory computer readable storage medium tangibly embodying program instructions implementing a method for injecting timing irregularities into test patterns self-generated by a device under test (DUT), the DUT comprising one or more output drivers and one or more input receivers and a pattern generator that generates the test patterns which are output onto the one or more output drivers, the method comprising:
obtaining timing irregularities by,
receiving event-based test data containing intentionally injected timing irregularities; and
extracting the timing irregularities from the event-based test data;
receiving the test patterns self-generated by the device under test driven from the one or more output drivers of the DUT;
injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein; and
applying the test patterns with timing irregularities injected therein to the one or more input receivers of the DUT.
10. The non-transitory computer readable storage medium of claim 9 , the method further comprising:
obtaining test results from the DUT, the test results indicating device operation based on the test patterns with timing irregularities injected therein received by the one or more input receivers of the DUT; and
determining whether the DUT is operating properly based on the test results.
11. The non-transitory computer readable storage medium of claim 9 , wherein:
the timing irregularities comprise clock period jitter.
12. The non-transitory computer readable storage medium of claim 9 , wherein:
the timing irregularities comprise clock period drift.