Dynamically reconfigurable precision signal delay test system for automatic test equipment
A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.
1. A programmable clock waveform generator circuit for an automated test equipment (ATE) system comprising:
a first serial in/parallel out shift register;
a first programmable delay element having an input and an output, wherein said input is coupled to said serial in/parallel out shift register; and
a first AND gate having an input coupled to said output of said programmable delay element wherein said AND gate generates a clock waveform signal based on data to re-program said first programmable delay element in between scan patterns stored in a pattern memory and wherein said clock waveform signal is for application to a tester access pin of said ATE system and wherein said pattern memory is coupled to said serial in/parallel out shift register and wherein said pattern memory contains said data to re-program said first programmable delay element in between scan patterns.
2. The circuit of claim 1 , wherein said pattern memory contains test pattern data for scan based testing.
3. The circuit of claim 1 , further comprising:
a second serial in/parallel out shift register coupled to said pattern memory;
a second programmable delay element having an input and an output, wherein said input is coupled to said second serial in/parallel out shift register; and
a second AND gate having an input, wherein said input is coupled to said output of said second programmable delay element and wherein said AND gate generates a timing signal based on data stored in said pattern memory, and,
an OR gate coupled to said first AND gate and to said second AND gate wherein said OR gate is for supplying said timing signal to said tester pin.
4. The circuit of claim 3 , further comprising a clock driver coupled to said OR gate.
5. A programmable clock waveform generator circuit for use in an Automatic Test Equipment (ATE) system comprising:
a plurality of clock signal waveform generators for generating a plurality of clock waveform signals each individually programmable and being individually enabled;
a selector circuit for selecting an output of said plurality of signal waveform generators, said selector circuit for supplying a selected clock waveform signal to a first tester pin of said ATE system; and
a pattern memory unit coupled to a serial in/parallel out shift register of each clock signal waveform generator to program said plurality of signal waveform generators and coupled to supply test pattern data to a plurality of tester access pins of said ATE system, said memory unit comprising test pattern data and also comprising timing data used to program said plurality of signal waveform generators in between scan patterns wherein said timing data used to program said plurality of signal waveform generators comprise relative timing positions for said plurality of signal waveform generators.
6. A programmable clock waveform generator circuit as described in claim 5 wherein said memory unit further comprises control data for enabling said plurality of signal waveform generators.
7. A programmable clock waveform generator circuit as described in claim 6 wherein each accessed location of said memory unit comprises associated pattern data, timing data and control data.
8. A programmable clock waveform generator circuit as described in claim 5 wherein said plurality of signal waveform generators are capable of generating signal waveform transitions with specified adjustable timing that is relative to previous signal waveform transitions of said tester pin.
9. A programmable clock waveform generator circuit as described in claim 5 wherein said plurality of signal waveform generators are capable of generating signal waveform transitions with specified adjustable timing that is relative to previous signal waveform transitions of another tester pin.
10. A programmable clock waveform generator circuit as described in claim 5 wherein one of said plurality of signal waveform generators is re-programmable by said memory unit while another of said plurality of signal waveform generators is enabled.
11. A programmable clock waveform generator circuit as described in claim 5 wherein each of said plurality of signal waveform generators comprise:
a circuit comprising an input for receiving serial programming data and a parallel output;
a delay element coupled to said parallel output; and
an enable circuit coupled to an output of said delay element.
12. A programmable clock waveform generator circuit for an automated test equipment (ATE) system comprising:
a plurality of individually programmable clock waveform generator circuits, each comprising a serial input and an output;
a pattern memory coupled to each of said serial inputs and containing scan data and also test data for programming said waveform generator circuits in between scan patterns wherein said memory also contains enable data for enabling one of said waveform generator circuits to drive a tester access pin and wherein said test data comprises values for specifying the relative timing positions for the signal waveform generator circuits; and
an enable circuit coupled to the outputs of said individually programmable clock waveform generator circuits for selecting an output for driving a said tester access pin of said ATE system.
13. The system of claim 12 , wherein said enable circuit comprises an OR gate.
14. The system of claim 12 , wherein each of said programmable clock waveform generator circuits comprise a respective programmable delay element.
15. The system of claim 14 , wherein each of said clock waveform generator circuits further comprise a respective serial in/parallel out shift register.