Evaluation of an output signal of a device under test
View Patent ↗The present invention relates to a method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, said method including the steps of: generating a difference signal representing the difference between said output signal of said Device Under Test and a reference signal, integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.
1. A method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, and wherein said output signal includes a sequence of bit levels, said method comprising steps of:
continuously comparing said output signal of said Device Under Test and a reference signal to generate a difference signal representing the differences between said output signal of said Device Under Test and said reference signal,
integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and
evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.
2. The method of claim 1 , wherein said evaluating step comprises a step of comparing said integrated difference signal with at least one comparative signal.
3. The method of claim 2 , wherein said comparing is performed continuously resulting in a continuous comparison signal, and that for evaluating of said output signal of said Device Under Test said continuous comparison signal is sampled at predetermined points in time.
4. The method of claim 1 , wherein said integrating of said difference signal is performed continuously.
5. The method of claim 1 , wherein said integrated difference signal is periodically reset to a predetermined value, and reset once in each clock period to the value zero.
6. The method of claim 1 , wherein said reference signal is a predetermined threshold value signal.
7. The method of claim 6 , wherein an output signal of said comparison is oversampled, and said integrating and evaluating are based on said oversampled output signal of said comparison of said output signal of said Device Under Test and said predetermined threshold value signal.
8. The method of claim 1 , wherein said reference signal is a binary signal representing a bit value expected for said output signal of said Device Under Test in said respective clock period.
9. The method of claim 8 , wherein low and/or high level of said binary signal can be adjusted.
10. A software program or product, stored in a non-transitory form on a data carrier, for executing a method for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, and wherein said output signal includes a sequence of bit levels, said method comprising steps of:
continuously comparing said output signal of said Device Under Test and a reference signal to generate a difference signal representing the differences between said output signal of said Device Under Test and said reference signal,
integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and
evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period, when running on a data processing system such as a computer.
11. A system for evaluating an output signal of a Device Under Test, wherein said Device Under Test outputs said output signal in response to an input signal provided by an Automated Test Equipment, and wherein said output signal includes a sequence of bit levels, said system comprising:
a generator for continuously comparing said output signal of said Device Under Test and a reference signal to generate a difference signal representing the differences between said output signal of said Device Under Test and said reference signal,
an integrator for integrating said difference signal during a clock period respectively, resulting in an integrated difference signal, and
an evaluator for evaluating said integrated difference signal with regard to a bit level to be assigned to said output signal of said Device Under Test during the respective clock period.