Method and apparatus for variable sigma-delta modulation

1. A sigma-delta modulation method, comprising:

partitioning a digital input signal comprising (M+L)-bit words into a less-significant bit signal and a more-significant bit signal wherein the partitioning comprises partitioning the digital input signal into the more-significant bit signal comprising M-bit words and the partitioning comprises partitioning the digital input signal into the less-significant bit signal comprising L-bit words;

performing a lower-order modulation of the less-significant bit signal to generate an intermediate output signal, the intermediate output signal comprises P-bit words, where P is less than L;

appending the intermediate output signal to the more-significant bit signal as less significant bits to form an intermediate input signal; and

performing a higher-order modulation of the intermediate output signal using a (M+P)-bit third order delta-sigma modulator to generate a digital output signal, the higher-order modulation of an order higher than the lower-order modulation.

2. A sigma-delta modulation method, comprising:

partitioning a digital input signal into a less-significant bit signal and a more-significant bit signal;

performing a lower-order modulation of the less-significant bit signal to generate an intermediate output signal;

appending the intermediate output signal to the more-significant bit signal as less significant bits to form an intermediate input signal; and

performing a higher-order modulation of the intermediate input signal to generate a digital output signal, the higher-order modulation of an order higher than the lower-order modulation wherein performing the higher-order modulation comprises performing the higher-order modulation using a third order delta-sigma modulator.

3. A sigma-delta modulator for modulating a digital input signal comprising (M+L)-bit words partitioned into less-significant bits and more-significant bits, the sigma-delta modulator comprising:

a lower-order modulator operable to modulate the L less-significant bits of the digital input signal to generate an intermediate output, the intermediate output comprises P-bit words, where P is less than L; and

a higher-order modulator of an order higher than the lower-order modulator operable to modulate the M more-significant bits of the digital input signal with the intermediate output appended thereto as less significant bits to generate a digital output signal, the higher-order modulator comprises a (M+P)-bit third-order sigma-delta modulator.

4. A sigma-delta modulator for modulating a digital input signal partitioned into less-significant bits and more-significant bits, the sigma-delta modulator comprising:

a lower-order modulator operable to modulate the less-significant bits of the digital input signal to generate an intermediate output; and

a higher-order modulator of an order higher than the lower-order modulator operable to modulate the more-significant bits of the digital input signal with the intermediate output appended thereto as less significant bits to generate a digital output signal wherein the higher-order modulator comprises a third-order sigma-delta modulator.

5. A Fractional_N phase-locked loop, comprising:

a phase comparator having a signal input, a feedback input, and an output, the signal input connected to receive a reference signal;

a voltage-controlled oscillator connected to the output of the phase comparator;

a divider connected between an output of the voltage controlled oscillator and the feedback input to the phase comparator, the divider having a variable divide ratio determined by a temporally-varying divide ratio sequence; and

a sigma-delta modulator for modulating a divide ratio control signal partitioned into less-significant bits and more-significant bits, comprising:

a lower-order modulator operable to modulate the less-significant bits of the divide ratio control signal to generate an intermediate output signal; and

a higher-order modulator of an order higher than the lower-order modulator, the higher-order modulator operable to modulate the more-significant bits of the divide ratio control signal with the intermediate output signal appended thereto as less significant bits to generate a sigma-delta modulated signal, the sigma-delta modulated signal constituting at least part of the temporally-varying divide ratio sequence.

6. The phase-locked loop as claimed in claim 5 , wherein the phase-locked loop further comprises:

a filter connected between the output of the phase comparator and an input of the voltage controlled oscillator for filtering substantially all quantization noise and frequency spurs generated by the divider in response to the temporally-varying divide ratio sequence.

7. The phase-locked loop as claimed in claim 5 , wherein the higher order modulator comprises a third-order sigma-delta modulator.

8. The phase-locked loop as claimed in claim 5 , wherein the lower-order modulator has an absence of multipliers.

9. The phase-locked loop as claimed in claim 5 , wherein the intermediate output signal has an average equal to a value of the less-significant bits.

10. The phase-locked loop as claimed in claim 5 , wherein:

the divide ratio control signal comprises an integer portion and a fractional portion;

the lower-order modulator is operable to modulate the less-significant bits in the fractional portion of the divide ratio control signal;

the higher-order modulator is operable to modulate the more-significant bits in the fractional portion of the divide ratio control signal with the intermediate output signal appended thereto as less significant bits; and

the phase-locked loop additionally comprises a divide ratio sequence generator operable to generate the temporally-varying divide ratio sequence from the integer portion of the divide ratio control signal and the sigma-delta modulated signal.

11. The phase-locked loop as claimed in claim 10 wherein:

the fractional portion of the divide ratio control signal comprises thirty-bit words each having 21 less-significant bits and 9 more-significant bits.