IP Library Granted Patent US 7,734,848
Granted Patent B2
US 7,734,848 · App. 11/595,640 · Granted Jun 8, 2010

System and method for frequency offset testing

Assignee: Verigy (Singapore) Pte. Ltd.
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Quick Facts
Patent No.
US 7,734,848
App. No.
11/595,640
Granted
Jun 8, 2010
Kind
B2
Abstract

Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.

Claims (36)

1. An automatic test equipment device, comprising:

an input receiving first data from an electronic device at a first frequency, the first frequency corresponding to a reference clock signal, and the first data being a repeatable waveform; and

an output transmitting second data to the electronic device at a second frequency, the second frequency being equal to a product of the first frequency and a frequency offset value, the frequency offset value being equal to a ratio of (i) an integer number of cycles of the repeatable waveform in a sampling window to (ii) a number of data points in the sampling window, and the frequency offset value also being equal to a ratio of (iii) the first frequency to (iv) a sampling frequency of the repeatable waveform used by the automatic test equipment, wherein the automatic test equipment device is configured to coherently sample the repeatable waveform at the sampling frequency over the sampling window.

2. The device according to claim 1 , wherein the electronic device is one of a video card, a sound card and a memory device.

3. The device according to claim 1 , wherein the electronic device utilizes a high-speed interface.

4. The device according to claim 3 , wherein the high-speed interface is one of PCI-Express, Serial ATA and SerDes.

5. The device according to claim 1 , wherein the repeatable waveform is one of (i) a pseudorandom binary sequence (PRBS) having a length of one of 2 7 −1 bits, 2 9 −1 bits, 2 10 −1 bits and 2 11 −1 bits, (ii) a forty bit compliance pattern and (iii) a repeatable data pattern.

6. The device according to claim 1 , further comprising:

a buffer storing the first data.

7. A method, comprising:

receiving first data from an electronic device at a first frequency, the first frequency corresponding to a reference clock signal, and the first data being a repeatable waveform;

sampling the received first data at a sampling frequency over a sampling window; and

transmitting second data to the electronic device at a second frequency, the second frequency being equal to a product of the first frequency and a frequency offset value, the frequency offset value being equal to a ratio of (i) an integer number of cycles of the repeatable waveform in the sampling window to (ii) a number of data points in the sampling window, and the frequency offset value also being equal to a ratio of (iii) the first frequency to (iv) a sampling frequency of the repeatable waveform used by the automatic test equipment.

8. The method according to claim 7 , further comprising:

storing the first data in a buffer; and

capturing the first data digitally.

9. The method according to claim 7 , further comprising:

determining a correlation between the first data and data transmitted by the electronic device.

10. The method according to claim 9 , further comprising:

determining whether the electronic device supports data exchange at the frequency offset value as a function of the correlation.

11. The method according to claim 10 , further comprising:

determining that the electronic device supports the data exchange at the frequency offset value when the correlation is indicative of one of (i) a complete match and (ii) a match within a predefined error bound.

12. The method according to claim 7 , further comprising:

reorganizing the first data into a complete waveform;

computing a derivative of the complete waveform to detect transitions therein; and

grouping the transitions to measure a jitter of the first data.

13. The method according to claim 12 , further comprising:

determining whether the electronic device supports data exchange at the frequency offset value as a function of the jitter.

14. The method according to claim 10 , further comprising:

determining that the electronic device supports the data exchange at the frequency offset value when the jitter is less than a predetermined jitter threshold.

15. The method according to claim 7 , wherein the first frequency corresponds to a reference clock signal received by the electronic device from an automatic test equipment device.

16. The method according to claim 7 , wherein the second data is a predefined data pattern.

17. A system, comprising:

an electronic device;

a first testing device providing a reference clock signal at a first frequency to the electronic device;

a second testing device receiving first data from the electronic device at the first frequency and transmitting second data to the electronic device at a second frequency, the second frequency being equal to a product of the first frequency and a frequency offset value, the first data being a repeatable waveform, the frequency offset value being equal to a ratio of (i) an integer number of cycles of the repeatable waveform in a sampling window to (ii) a number of data points in the sampling window, and the frequency offset value also being equal to a ratio of (iii) the first frequency to (iv) a sampling frequency of the repeatable waveform used by the automatic test equipment, wherein the second testing device is configured to coherently sample the repeatable waveform at the sampling frequency over the sampling window.

Assignments (5)
CHANGE OF ADDRESS Recorded Dec 18, 2018
From: ADVANTEST CORPORATION
To: ADVANTEST CORPORATION
Reel/Frame 047987/0626 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 035371 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 14, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035425/0768 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035371/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2012
From: VERIGY (SINGAPORE) PTE LTD
To: ADVANTEST (SINGAPORE) PTE LTD
Reel/Frame 027896/0018 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2007
From: LIU, JINLEI
To: VERIGY (SINGAPORE) PTE. LTD
Reel/Frame 019386/0529 →
Continuity (1)
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