Polynomial fit for jitter separation
View Patent ↗A method for determining the amount of deterministic jitter and random jitter in a digital signal having transitions between logical levels, the method comprising the steps of: providing said digital signal, determining a plurality of bit error rate values, each bit error rate value being associated with one of a plurality of successive timing points, and each bit error rate value being derived from a comparison of a result of a detection of a transition occurring in the digital signal cumulatively prior to its associated timing point with an expected signal, applying a polynomial fit in time to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and deriving the amount each of said deterministic and said random jitter from said polynomial coefficients.
1. A method for determining the amount of deterministic jitter and random jitter in a digital signal having transitions between logical levels, the method comprising the steps of:
a) determining a plurality of bit error rate values, each bit error rate value being associated with one of a plurality of successive timing points,
b) applying a polynomial fit to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and
c) deriving the amount each of said deterministic and said random jitter from said polynomial coefficients.
2. The method according to claim 1 ,
wherein each bit error rate value is derived from a comparison of a result of a detection of a transition occurring in the digital signal cumulatively prior to its associated timing point with an expected signal.
3. The method according to claim 1 ,
wherein said polynomial fit is applied to said plurality of bit error rate values with respect to the time coordinate.
4. The method according to claim 1 ,
wherein prior to applying said polynomial fit, each of said bit error rate values is transformed by:
(1.) calculating a negative logarithm of each of said determined bit error rate values,
(2.) calculating a square-root of each of said bit error rate values calculated in step (1.).
5. The method according to claim 4 ,
wherein said polynomial fit to said transformed bit error rate values is of first order in time for providing a trendline to the bit error rate value data.
6. The method according to claim 5 , wherein:
a first constant baseline corresponding to a probability of an occurrence of a bit error event of 0.5 is determined;
said trendline is extrapolated to determine a crossover point with said constant baseline;
a timing point is determined being associated with said crossover point;
the amount of deterministic jitter is derived from a comparison of said determined timing point with an expected timing point for a logical level transition of said digital signal.
7. The method according to claim 5 , wherein:
a slope of said trendline is determined,
the amount of random jitter is calculated from said slope.
8. The method according to claim 5 ,
wherein an amount of total jitter is determined from extrapolating said trendline to a crossover point with a second baseline being associated with a bit error rate value of 10 −12.
9. The method according to claim 1 ,
wherein said polynomial fit to said bit error rate values is performed by means of linear regression.
10. Method according to claim 8 ,
wherein each of said timing points is selected such as to provide bit error rate values, which are prior to performing any transformation larger than 10 −6 and smaller than 10 −4 .
11. Method according to claim 10 ,
wherein three timing points are selected to determine three bit error rate values.
12. The method according to claim 1 ,
wherein said polynomial fit is of second order.
13. An arrangement for determining the amount of deterministic jitter and random jitter in a digital signal having transitions between logical levels, comprising:
a measurement unit for determining a plurality of bit error rate values, each bit error rate value being associated with one of a plurality of successive timing points,
a data processing unit capable of applying a polynomial fit to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and for deriving the amount each of said deterministic and said random jitter from said polynomial coefficients.
14. A bit error rate tester, comprising:
a measurement device for measuring a plurality of bit error rate values in a digital signal having transitions between logical levels, each bit error rate value being associated with one of a plurality of successive timing points,
a data processing unit capable of applying a polynomial fit to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and for deriving the amount each of deterministic and random jitter from said polynomial coefficients.
15. A program storage medium, preferably stored on a data carrier, embodying a program of instructions executable on a data processing system such as a computer to perform method steps for determining the amount of deterministic jitter and random jitter in a digital signal having transitions between logical levels, said method steps comprising:
a) determining a plurality of bit error rate values, each bit error rate value being associated with one of a plurality of successive timing points,
b) applying a polynomial fit to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and
c) deriving the amount each of said deterministic and said random jitter from said polynomial coefficients.