Systems and methods for testing a device-under-test

1. A method for testing a device-under-test (DUT), the method comprising:

examining a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data entries and a second plurality of data entries, the first plurality of data entries corresponding to a first plurality of DUT pins, and the second plurality of data entries corresponding to a second plurality of DUT pins;

determining whether each of the data entries of the test data file corresponds to a pin of the first plurality of DUT pins or to a pin of the second plurality of DUT pins, wherein the first plurality of DUT pins are scan pins and the second plurality of DUT pins are non-scan pins;

separating the first plurality of data entries from the second plurality of data entries;

communicating the first plurality of data entries to the first plurality of DUT pins; and

communicating the second plurality of data entries to the second plurality of DUT pins.

2. The method of claim 1 , wherein the first plurality of data entries have at least one different property than the second plurality of data entries.

3. The method of claim 2 , wherein the at least one different property includes timing complexity.

4. The method of claim 2 , wherein the at least one different property includes vector data volume.

5. The method of claim 2 , wherein the at least one different property includes repetitive data patterns.

6. The method of claim 1 , further comprising:

formatting the first plurality of data entries independently from the second plurality of data entries.

7. The method of claim 1 , wherein the test data file is one of a STIL (standard test interface language) file and a WGL (waveform generation language) file.

8. The method of claim 1 , further comprising:

identifying the first plurality of DUT pins; and

storing information identifying the first plurality of DUT pins in memory.

9. The method of claim 8 , further comprising:

providing the information to a module configured to format the test data file.

10. The method of claim 1 , further comprising:

providing the first plurality of data entries to the first plurality of DUT pins in a first timing domain; and

providing the second plurality of data entries to the second plurality of DUT pins in a second timing domain;

wherein the first timing domain is different from the second timing domain.

11. A system for testing a device-under-test (DUT), the system comprising:

memory operative to store a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data entries and a second plurality of data entries, the first plurality of data entries corresponding to a first plurality of DUT pins, and the second plurality of data entries corresponding to a second plurality of DUT pins; and

a processor that is programmed to determine whether each of the data entries of the test data file corresponds to a pin of the first plurality of DUT pins or to a pin of the second plurality of DUT pins, wherein the first plurality of DUT pins are associated with scan pins and the second plurality of DUT pins are associated with non-scan pins, the processor further programmed to separate the first plurality of data entries from the second plurality of data entries.

12. The system of claim 11 , wherein the processor is further programmed to provide the first plurality of data entries and the second plurality of data entries to a device configured to format the first plurality of data entries independently from the second plurality of data entries.

13. The system of claim 11 ,

wherein the processor is further programmed to identify the first plurality of DUT pins based on information contained in the test data file, and to store information identifying the first plurality of DUT pins in memory.

14. The system of claim 13 , wherein the processor is programmed to provide the information identifying the first plurality of DUT pins to a device configured to format test data.

15. A system for testing a device-under-test (DUT), the system comprising:

means for storing a test data file that includes test data configured to enable testing the DUT, the test data file including a first plurality of data entries and a second plurality of data entries, the first plurality of data entries corresponding to a first plurality of DUT pins, and the second plurality of data entries corresponding to a second plurality of DUT pins;

means for determining whether each of the data entries of the test data file corresponds to a pin of the first plurality of DUT pins or to a pin of the second plurality of DUT pins, wherein the first plurality of DUT pins are scan pins and the second plurality of DUT pins are non-scan pins; and

means for separating the first plurality of data entries from the second plurality of data entries, wherein the first plurality of data entries are communicated to the first plurality of DUT pins and the second plurality of data entries are communicated to the second plurality of DUT pins.

16. The system of claim 15 , wherein the first plurality of data entries have at least one different property than the second plurality of data entries, the at least one different property including timing complexity, vector data volume, and repetitive data patterns.

17. The system of claim 15 , further comprising:

means for formatting the first plurality of data entries independently from the second plurality of data entries.

18. The system of claim 15 , wherein the test data file is one of a STIL (standard test interface language) file and a WGL (waveform generation language) file.

19. The system of claim 15 , wherein the means for formatting is configured to operate in a first timing domain to enable the first plurality of data entries to be provided to the first plurality of DUT pins, and to operate in a second timing domain to enable the second plurality of data entries to be provided to the second plurality of DUT pins, wherein the second timing domain is different from the first timing domain.

20. The system of claim 15 , further comprising:

means for identifying the first plurality of DUT pins and for storing the information identifying the first plurality of DUT pins in the storing means.