Diagnostic information capture from logic devices with built-in self test

1. A method of obtaining diagnostic information from a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, the method comprising:

using the scan chains, applying a stimulus vector to the logic circuits, capturing responses of the logic circuits to the stimulus vector and shifting the captured responses toward outputs of the scan chains;

generating a representative signature representing captured responses output by the scan chains;

concurrently with the generating, temporarily storing the captured responses output by the scan chains such that no more than a most-recently output subset of the captured responses is stored, the subset consisting of fewer than all of the captured responses;

determining whether the representative signature is a fault-indicating representative signature; and

when the representative signature is a fault-indicating representative signature, outputting at least some of the temporarily stored captured responses.

2. The method of claim 1 , in which:

the generating introduces latency; and

the maximum number of responses temporarily stored depends on the latency.

3. The method of claim 1 , additionally comprising, when the representative signature is a fault-indicating representative signature, resetting the generating.

4. The method of claim 1 , additionally comprising, when the representative signature is a fault-indicating representative signature, suspending operation of the BIST.

5. The method of claim 1 , additionally comprising:

connecting the logic device to automatic test equipment; and

when the determining determines that the representative signature is a fault- indicating representative signature, causing the automatic test equipment to receive the at least some of the temporarily stored captured responses.

6. The method of claim 5 , in which the causing comprises providing an interrupt to the automatic test equipment.

7. The method of claim 5 , additionally comprising waiting for the ATE to indicate readiness to receive the temporarily stored captured responses.

8. The method of claim 7 , additionally comprising, during the wait for the ATE to indicate readiness to receive the output responses, continuing to:

shift the captured responses towards the outputs of the scan chains, generate the representative signature, and temporarily store the captured responses output by the scan chains.

9. The method of claim 1 , in which the determining comprises comparing the representative signature with a corresponding expected signature.

10. The method of claim 9 , in which the comparing comprises performing a multi-bit comparison.

11. The method of claim 10 , in which:

the representative signature and the corresponding expected signature are multi-bit values; and

the comparing comprises receiving the multi-bit expected signature serially.

12. The method of claim 9 , in which the comparing comprises generating the corresponding expected signature within the logic device.

13. A device, comprising:

logic circuits;

a built-in self-test system (BIST) comprising a digital signature generator and scan chains coupled to the logic circuits, the scan chains having outputs coupled to the digital signature generator, the scan chains operable to apply a stimulus vector to the logic circuits, to capture responses of the logic circuit to the stimulus vector and to shift the captured responses toward the outputs of the scan chains, the digital signature generator operable to output a representative signature representing the captured responses output by the scan chains; and

a diagnostic information collector, comprising:

a comparator comprising an output and a representative signature input, the representative signature input coupled to the digital signature generator, the output changing to a fault-indicating state when the representative signature is a fault-indicating representative signature, and

a buffer coupled to the outputs of the scan chains and operable concurrently with the digital signature generator to store temporarily the captured responses output by the scan chains such that a most-recently stored subset of the captured responses output by the scan chains is stored therein, the subset consisting of fewer than all of the captured responses generated in response to the stimulus vector, the buffer additionally operable in response to the fault-indicating state at the output of the comparator to output at least some of the temporarily stored captured responses as diagnostic information.

14. The device of claim 13 , in which:

the comparator additionally comprises an expected signature input; and

the device additionally comprises an expected signature source coupled to the expected signature input of the comparator.

15. The device of claim 14 , in which:

the digital signature generator generates multi-bit representative signatures and the expected signature source provides corresponding multi-bit expected signatures; and

the expected signature source comprises an input at which multi-bit expected signature information is received serially.

16. The device of claim 14 , in which the expected signature source comprises an expected signature generator internal to the logic circuits.

17. The device of claim 13 , in which:

the output of the comparator is additionally coupled to the digital signature generator; and

the fault-indicating state at the output of the comparator causes the digital signature generator to be reset to generate a non fault-indicating representative signature.

18. The device of claim 13 , in which:

the output of the comparator is coupled to the BIST; and

the fault-indicating state at the output of the comparator causes the BIST to suspend operation.

19. The device of claim 13 , additionally comprising multiplexers interposed between the outputs of the scan chains and the digital signature generator.

20. The device of claim 13 , in which the digital signature generator comprises one of a single output multiple-input shift register, a multiple-input shift register having multiple output taps, and an X-Compactor.

21. A system, comprising:

automatic test equipment; and

a logic device under test connected to the automatic test equipment, the logic device comprising:

logic circuits,

a built-in self-test system (BIST) comprising a digital signature generator and scan chains coupled to the logic circuits, the scan chains having outputs coupled to the digital signature generator, the scan chains operable to shift a stimulus vector into the logic circuits, to capture responses of the logic circuit to the stimulus vector and to shift the captured responses toward the outputs of the scan chains, the digital signature generator operable to generate a representative signature representing the captured responses output by the scan chains, and

a diagnostic information collector, comprising:

a comparator comprising an output and a representative signature input, the representative signature input coupled to the digital signature generator, the output changing to a fault-indicating state when the representative signature is a fault-indicating representative signature; and

a buffer coupled to the outputs of the scan chains and operable concurrently with the digital signature generator to store temporarily the captured responses output by the scan chains such that a most-recently stored subset of the captured responses output by the scan chains is stored therein, the subset consisting of fewer than all of the captured responses generated in response to the stimulus vector, the buffer additionally operable in response to the fault-indicating state at the output of the comparator to output at least some of the temporarily stored captured responses as diagnostic information.

22. The device of claim 21 , in which the fault-indicating state of the output of the comparator causes the automatic test equipment to receive the responses output from the buffer.