Apparatus for locating a defect in a scan chain while testing digital logic

1. An apparatus for locating a stuck-at defect in a scan chain of a semiconductor device under test controlled by a scan clock during a test applying a plurality of scan patterns, comprising:

means for representing a current bit position of a scan pattern being shifted out of a scan chain;

means for storing the current bit position when the current bit position is a largest bit position having the complement of a stuck-at value being tested for at an output of the scan chain, wherein each bit position of the scan pattern being shifted out of the scan chain has a larger bit position than a previous bit position shifted out of the scan chain; and

means for determining if the current bit position is greater than the largest bit position stored in a scan test.

2. The apparatus of claim 1 , further comprising means for resetting the counter “C” at the start of each pattern and means for incrementing the value of the counter “C” on each data cycle.

3. An apparatus, comprising:

at least one register;

a counter “C” coupled to the at least one register;

at least one magnitude comparator to which the counter is coupled, the magnitude comparator further coupled to the register whereby the magnitude comparator emits a signal that changes from a digital “0” to “1” state when the value of the counter “C” is greater than the value of the register; and

means for loading the register with the value of the counter “C” when the value of the counter “C” is greater than the value of the register and the scan output data has the value of a stuck-at defect being tested for.

4. An apparatus for dynamically determining the last data state transition sensed while unloading a scan chain, comprising:

means for observing the data state of the scan output;

means for recording the bit position of each scan output;

means for loading a first register with the bit position of the last scan output “0”; and

means for loading a second register with the bit position of the last scan output “1”.

5. A methods, comprising the steps of:

performing a “Chain Integrity” test for a scan chain of a device under test, the “Chain Integrity” test comprising shifting an arbitrary data pattern into a scan in pin of the scan chain and observing a scan out pin of the scan chain to confirm that the arbitrary data pattern appears at the scan out pin; and

after performing the “Chain Integrity” test, performing at least one of the following:

loading standard scan test patterns for combinational logic of the device under test, into the scan chain, if the “Chain Integrity” test passes;

if the “Chain Integrity” test fails and the observed data output pattern at the scan out pin during the “Chain Integrity” test is all 0' s, then applying standard combinational test patterns to the scan chain and determining, by monitoring a current bit position of a scan pattern shifted out of the scan out pin, a bit location of a last “1” data state at the scan out pin;

if the “Chain Integrity” test fails and the observed data output pattern at the scan out pin during the “Chain Integrity” test is all 1's, then applying standard combinational test patterns to the scan chain and determining, by monitoring a current bit position of a scan pattern shifted out of the scan out pin, a bit location of a last “0” data state at the scan out pin; and

if the “Chain Integrity” test fails and the observed data output pattern at the scan out pin during the “Chain Integrity” test consists of both 0 and 1 data states, noting that a defect is not a “stuck-at” defect.

6. The method of claim 5 ,further comprising:

resetting a value of a counter at a start of each scan pattern load;

incrementing a counter on each data cycle of a scan pattern shift;

loading a first register with the value of the counter when the scan output data is “0” and the value of the counter is greater than the last stored value in the first register, and loading a second register with the value of the counter when the scan output data is “1” and the value of the counter is greater than the last stored value in the second register; and

reporting a lower value of the two registers as a location abutting a blockage in the scan chain.