Method and apparatus for determining a minimum/maximum of a plurality of binary values

1. A method for determining a minimum/maximum of a plurality of binary values held by a plurality of processor memories or memories associated with respective processors, the method comprising:

determining a bit position in the plurality of binary values subsequent to which all bit values are the same, wherein the determining including,

commonly reading all binary values from all memories and generating a bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of binary values and based on the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values, determining the bit location in the plurality of binary values subsequent to which all bit values are the same;

selecting from the plurality of binary values, those binary values, the bit value of which at the bit position determined in the determining and all subsequent bit positions, if any, comprises a predetermined value;

repeating the determining and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.

2. The method of claim 1 , wherein the predefined value is “1” in case a maximum is to be determined, and wherein the predetermined value is “0” in case a minimum is to be determined.

3. The method of claim 1 , wherein for generating a subsequent bitwise OR combination and a subsequent bit-wise AND combination the selecting comprises:

in case the bit value of an original binary value at the bit position determined in the determining corresponds to the predetermined value, selecting the original binary values, and

otherwise selecting a modified value; and

wherein repeating the determining is based on the subsequent bit-wise OR combination and the subsequent bit-wise AND combination.

4. The method of claim 3 , wherein

for the subsequent bit-wise OR combination the modified value is formed by the up to now known bits of the minimum/maximum and the remaining bits of the existing bit-wise AND combination, and

for the subsequent bit-wise AND combination, the modified value is formed by the up to now known bits of the minimum/maximum and the remaining, bits of the existing bit-wise OR combination.

5. The method of claim 4 , wherein

the determining comprises:

communicating the bit-wise OR combination and the bit-wise AND combination to the memories; and

the selecting comprises:

communicating the up to now known bit values of the minimum/maximum to the memories,

for the subsequent bit-wise OR combination, instructing each memory to return the original value, in case the bit value at the bit position determined in the determining and all subsequent bit positions, if any, correspond to the up to now known bit values of the minimum/maximum, and

otherwise, return the up to now known hit values of the minimum/maximum and the bit values of the retraining bit positions of the existing bit-wise AND combinations, and

for the subsequent bit-wise AND combination, instructing each memory to return the original value, in case the bit value at the bit position determined in the determining, and all subsequent bit positions, if any, correspond to the up to now known bit values of the minimum/maximum, and

otherwise, return the up to now known bit values of the minimum/maximum and the bit values of the remaining bit positions of the existing bit-wise OR combination.

6. A non-transitory computer storage medium comprising a computer readable program code for carrying out, when executing the program code by a processor, a method for determining a minimum/maximum of a plurality of binary values held by a plurality of processor memories or memories associated with respective processors, the method comprising:

determining a bit position in the plurality of binary values, subsequent to which all bit values are the same, wherein the determining initially including,

commonly reading all binary values from all memories and generating a bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of binary values, and based on a comparison between the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values, determining the bit location in the plurality of binary values subsequent to which all bit values are the same;

selecting from the plurality of binary values, those binary values, the bit value of which at the bit location determined based upon the comparison between the bit-wise OR combination and the bit-wise AND combination, and all subsequent bit positions if any, comprises a predetermined value;

repeating the determining and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.

7. A non-transitory computer readable medium, comprising a computer readable program code for carrying out, when executing the program code by a processor, a method for determining a minimum/maximum of a plurality of binary values held by a plurality of processor memories or memories associated with respective processors, the method comprising:

commonly reading all binary values from all memories;

generating a bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of binary values;

determining the bit location in the plurality of binary values subsequent to which all bit values are the same, based on a comparison between the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values;

selecting from the plurality of binary values, those binary values, the bit value of which at the determined bit location, and all subsequent bit positions if any, comprises a predetermined value;

repeating the determining and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.

8. A non-transitory computer readable medium, comprising a program code for carrying out, when executing the program code by a processor, a method for determining a minimum/maximum of a plurality of binary values held by as plurality of processor memories or memories associated with respective processors, the method comprising:

determining a bit position in the plurality of binary values subsequent to which all bit values are the same, wherein the determining initially comprises:

commonly reading all binary values from all memories and generating a bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of binary values, and determining the bit location in the plurality of binary values subsequent to which all bit values are the same based on a comparison between the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values;

selecting from the plurality of binary values, those binary values, the bit value of which at the bit location determined in the determining and all subsequent bit positions, if any, comprises a predetermined value;

repeating the determining and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.

9. A system comprising:

a central processor;

a logic coupled to the central processor and configured to output a bit-wise OR combination and a bit-wise AND combination of a plurality of input values to the central processor; and

a plurality of memories associated with respective processors, each of the memories being coupled to the logic and configured to hold one of the plurality of binary values, wherein the central processor is configured to operate in accordance with a method for determining a minimum/maximum of a plurality of binary values held by a plurality of processor memories or memories associated with respective processors, the method including

determining a bit position in the plurality of binary values subsequent to which all bit values are the same, wherein the determining initially including,

commonly reading all binary values from all memories and generating bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of him values, and

determining the bit location in the plurality of binary values subsequent to which all bit values are the same based on a comparison between the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values;

selecting from the plurality of binary values, those binary values, the bit value of which at the bit location determined in the determining and all subsequent bit positions, if any, comprises a predetermined value;

repeating the determining and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.

10. The system of claim 9 , wherein the logic, is implemented by the central processor.

11. The system of claim 9 being a tester for testing electronic devices, wherein the binary values represent test results.

12. An apparatus comprising:

a plurality of processor memories or memories associated with respective processors; and

a processor configured to operate in accordance with a method for determining a minimum/maximum of a plurality of binary values held by the plurality of processor memories or memories associated with respective processors, the method including,

commonly reading all binary values from all memories;

generating a bit-wise OR combination of the commonly read plurality of binary values and a bit-wise AND combination of the commonly read plurality of binary values;

determining the bit location in the plurality of binary values subsequent to which all bit values are the same based on a comparison between the bit-wise OR combination and the bit-wise AND combination of the commonly read plurality of binary values;

selecting from the plurality of binary values, those binary values, the bit value of which at the determined bit location, and all subsequent bit positions if any, comprises a predetermined value;

repeating, the determining, and selecting, wherein the determining is repeated on the basis of the binary values selected in the selecting, until only one selected binary value, or a plurality of matching binary values, remain; and

providing the remaining binary value as the minimum/maximum.